[all-commits] [llvm/llvm-project] 847c78: [RISCV] Add scheduler model for sifive-p450. (#77989)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 847c78726920e4a29d71bdc3a46c92a0bc26bfc4
      https://github.com/llvm/llvm-project/commit/847c78726920e4a29d71bdc3a46c92a0bc26bfc4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-16 (Tue, 16 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

  Log Message:
  -----------
  [RISCV] Add scheduler model for sifive-p450. (#77989)

This is a slightly cleaned up version of what we've been using in our
downstream toolchain.