[all-commits] [llvm/llvm-project] 3ac9fe: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a
      https://github.com/llvm/llvm-project/commit/3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a
  Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
  Date:   2024-01-16 (Tue, 16 Jan 2024)

  Changed paths:
    M clang/docs/ReleaseNotes.rst
    M clang/lib/Basic/Targets/RISCV.cpp
    M clang/lib/Basic/Targets/RISCV.h
    M clang/lib/CodeGen/CodeGenModule.cpp
    M clang/lib/CodeGen/TargetInfo.h
    M clang/lib/CodeGen/Targets/RISCV.cpp
    M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
    M clang/test/CodeGen/RISCV/riscv32-abi.c
    A clang/test/CodeGen/RISCV/riscv32-ilp32e-error.c
    M clang/test/CodeGen/RISCV/riscv32-vararg.c
    M clang/test/CodeGen/RISCV/riscv64-abi.c
    M clang/test/CodeGen/RISCV/riscv64-vararg.c
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/Support/RISCVAttributes.h
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
    M llvm/lib/Target/RISCV/RISCVCallingConv.td
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVFrameLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
    M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
    A llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
    A llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
    A llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
    M llvm/test/CodeGen/RISCV/interrupt-attr.ll
    A llvm/test/CodeGen/RISCV/rv32e.ll
    A llvm/test/CodeGen/RISCV/rv64e.ll
    R llvm/test/CodeGen/RISCV/rve.ll
    M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
    M llvm/test/CodeGen/RISCV/stack-realignment.ll
    M llvm/test/CodeGen/RISCV/target-abi-valid.ll
    A llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
    M llvm/test/CodeGen/RISCV/vararg.ll
    M llvm/test/MC/RISCV/option-invalid.s
    M llvm/test/MC/RISCV/target-abi-invalid.s

  Log Message:
  -----------
  [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)

This commit includes the necessary changes to clang and LLVM to support
codegen of `RVE` and the `ilp32e`/`lp64e` ABIs.

The differences between `RVE` and `RVI` are:
* `RVE` reduces the integer register count to 16(x0-x16).
* The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits.

`RVE` can be combined with all current standard extensions.

The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are:
* Only 6 integer argument registers (rather than 8).
* Only 2 callee-saved registers (rather than 12).
* A Stack Alignment of 32bits (rather than 128bits).
* ilp32e isn't compatible with D ISA extension.

If `ilp32e` or `lp64` is used with an ISA that has any of the registers
x16-x31 and f0-f31, then these registers are considered temporaries.

To be compatible with the implementation of ilp32e in GCC, we don't use
aligned registers to pass variadic arguments and set stack alignment\
to 4-bytes for types with length of 2*XLEN.

FastCC is also supported on RVE, while GHC isn't since there is only one
avaiable register.

Differential Revision: https://reviews.llvm.org/D70401