[all-commits] [llvm/llvm-project] 286a36: [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo var...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 286a366d057112a112507b9e34c68d35b3b820f7
      https://github.com/llvm/llvm-project/commit/286a366d057112a112507b9e34c68d35b3b820f7
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-16 (Tue, 16 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
    M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)

vmv.s.x and vmv.x.s ignore LMUL, so we can replace the PseudoVMV_S_X_MX
and
PseudoVMV_X_S_MX with just one pseudo each. These pseudos use the VR
register
class (just like the actual instruction), so we now only have TableGen
patterns for vectors of LMUL <= 1.
We now rely on the existing combines that shrink LMUL down to 1 for
vmv_s_x_vl (and vfmv_s_f_vl). We could look into removing these combines
later and just inserting the nodes with the correct type in a later
patch.

The test diff is due to the fact that a PseudoVMV_S_X/PsuedoVMV_X_S no
longer
carries any information about LMUL, so if it's the only vector pseudo
instruction in a block then it now defaults to LMUL=1.