[all-commits] [llvm/llvm-project] 0cf768: [RISCV] Handle disjoint or in RISCVGatherScatterLo...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0cf768e7f12dfb581fbae40a3b9b77f6c4533c29
      https://github.com/llvm/llvm-project/commit/0cf768e7f12dfb581fbae40a3b9b77f6c4533c29
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-15 (Mon, 15 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll

  Log Message:
  -----------
  [RISCV] Handle disjoint or in RISCVGatherScatterLowering (#77800)

This patch adds support for the disjoint flag in the non-recursive case,
as well as adding an additional check for it in the recursive case. Note
that haveNoCommonBitsSet should be equivalent to having the disjoint
flag set, and the check can be removed in a follow-up patch.

Co-authored-by: Philip Reames <preames at rivosinc.com>

---------

Co-authored-by: Philip Reames <preames at rivosinc.com>