[all-commits] [llvm/llvm-project] 114e6d: [RISCV] Add test for strided gather with recursive...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 114e6d7ba02f090117f2cb1ffeb9027cf80f335b
      https://github.com/llvm/llvm-project/commit/114e6d7ba02f090117f2cb1ffeb9027cf80f335b
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-12 (Fri, 12 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/strided-load-store.ll

  Log Message:
  -----------
  [RISCV] Add test for strided gather with recursive disjoint or. NFC

This already gets converted to a strided intrinsic because we currently call
haveNoCommonBitsSet when checking or instructions, but an upcoming patch will
change this logic and we want to preserve this case.

Note that this IR is in the form that comes from instcombine. The splats need
to be inline constexprs, otherwise isSplatValue() will fail. (It can't
currently handle splats where the shufflevector is an instruction, and the
insertelement is a constexpr.