[all-commits] [llvm/llvm-project] ef4a95: [AArch64] Enable certain instruction aliases for S...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ef4a95c86210e11cf4bfbf545c2f859b5c772888
      https://github.com/llvm/llvm-project/commit/ef4a95c86210e11cf4bfbf545c2f859b5c772888
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/MC/AArch64/SVE/predicate-as-counter-aliases.s

  Log Message:
  -----------
  [AArch64] Enable certain instruction aliases for SVE/SME (#77745)

Several SVE instruction aliases accept predicate-as-counter register
names as a convenience. These ought to be enabled with SVE/SME because
the underlying encoding is valid and it's required by Arm ARM.