[all-commits] [llvm/llvm-project] 75d820: [AArch64] MI Scheduler: create more LDP/STP pairs ...

[Sjoerd Meijer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 75d820dcdd868b8ab6c12ff62f90216ad377ce20
      https://github.com/llvm/llvm-project/commit/75d820dcdd868b8ab6c12ff62f90216ad377ce20
  Author: Sjoerd Meijer <smeijer at nvidia.com>
  Date:   2024-01-11 (Thu, 11 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
    M llvm/test/CodeGen/AArch64/machine-combiner-copy.ll

  Log Message:
  -----------
  [AArch64] MI Scheduler: create more LDP/STP pairs (#77565)

Target hook `canPairLdStOpc` is missing quite a few opcodes for which
LDPs/STPs can created. I was hoping that it would not be necessary to
add these missing opcodes here and that the attached motivating test
case would be handled by the LoadStoreOptimiser (especially after
#71908), but it's not. The problem is that after register allocation
some things are a lot harder to do. Consider this for the motivating
example

```
[1] renamable $q1 = LDURQi renamable $x9, -16 :: (load (s128) from %ir.r51, align 8, !tbaa !0)
[2] renamable $q2 = LDURQi renamable $x0, -16 :: (load (s128) from %ir.r53, align 8, !tbaa !4)
[3] renamable $q1 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMLSv2f64 killed renamable $q1(tied-def 0), killed renamable $q2, renamable $q0, implicit $fpcr
[4] STURQi killed renamable $q1, renamable $x9, -16 :: (store (s128) into %ir.r51, align 1, !tbaa !0)
[5] renamable $q1 = LDRQui renamable $x9, 0 :: (load (s128) from %ir.r.G0001_609.0, align 8, !tbaa !0)
```
We can't combine the the load in line [5] into the load on [1]:
regisister q1 is used in between. And we can can't combine [1] into 
[5]: it is aliasing with the STR on line [4].

So, adding some missing opcodes here seems the best/easiest approach.
I will follow up to add some more missing cases here.