[all-commits] [llvm/llvm-project] 03be44: [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-deb...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 03be448cce8b6a5f1aa36fc1b316508b08b3aa9f
      https://github.com/llvm/llvm-project/commit/03be448cce8b6a5f1aa36fc1b316508b08b3aa9f
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/Generic/live-debug-label.ll

  Log Message:
  -----------
  [RISCV][AMDGPU] Mark test/CodeGen/Generic/live-debug-label.ll XFAIL for RISCV and AMDGPU (#77631)

Both RISC-V and AMDGPU(GCN) deploy two VirtRegRewriter in their codegen
pipeline. This test prematurely stops at the first one, which doesn't
cleanup the virtual register map and cause an assertion failure. Ideally
we can solve this by teaching `-stop-after` how to stop at the last
instance of a Pass, but we're just marking XFAIL for these two targets
for now.