[all-commits] [llvm/llvm-project] 0a1b06: [RISCV] Support isel for Zacas for XLen and i32. (...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a1b066bbaf7e3800f47697231d7e1e91744ecbf
      https://github.com/llvm/llvm-project/commit/0a1b066bbaf7e3800f47697231d7e1e91744ecbf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll
    M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll

  Log Message:
  -----------
  [RISCV] Support isel for Zacas for XLen and i32. (#77666)

This adds new isel patterns for Zacas that take priority over the
pseudoinstructions we use for the A extension.

Support for 2x XLen types will come in a separate patch since they need
to be done differently.