[all-commits] [llvm/llvm-project] c053e9: [RISCV] Re-implement Zacas MC layer support to mak...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c053e9f0f4b56a56582ad149a8c89434126eff7f
      https://github.com/llvm/llvm-project/commit/c053e9f0f4b56a56582ad149a8c89434126eff7f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
    M llvm/test/MC/RISCV/rv32zacas-invalid.s
    M llvm/test/MC/RISCV/rv64zacas-invalid.s

  Log Message:
  -----------
  [RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#77418)

This changes the register class to GPRPair and adds the destination
register as a source with a tied operand constraint.
    
Parsing for the paired register is done with a custom parser that
checks for even register and converts it to its pair version. A
bit of care needs to be taken so that we only parse as a pair register
based on which instruction we're parsing and the mode in the subtarget.
This allows amocas.w to be parsed correcty in both modes.
    
I've added a FIXME to note that we should be creating pair registers
for Zdinx on RV32 to match the instructions CodeGen generates.