[all-commits] [llvm/llvm-project] e42a70: [RISCV][GISel] IRTranslate and Legalize some instr...

[Jiahan Xie via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e42a70afab47a7a9e76a40bb553eee458a5f18ae
      https://github.com/llvm/llvm-project/commit/e42a70afab47a7a9e76a40bb553eee458a5f18ae
  Author: jiahanxie353 <jx353 at cornell.edu>
  Date:   2024-01-09 (Tue, 09 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-alu.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add-zve32x.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-add.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-and.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-or.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-sub.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-xor.mir

  Log Message:
  -----------
  [RISCV][GISel] IRTranslate and Legalize some instructions with scalable vector type

* Add IRTranslate tests for ADD, SUB, AND, OR, and XOR with scalable
  vector types to show that they work as expected.
* Legalize G_ADD, G_SUB, G_AND, G_OR, and G_XOR of scalable vector
  type for the RISC-V vector extension.