[all-commits] [llvm/llvm-project] 661558: [PowerPC] Make verifier happy when lowering `llvm....

[Kai Luo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6615581526f62a00833b2d60cc31f7f12497b5ff
      https://github.com/llvm/llvm-project/commit/6615581526f62a00833b2d60cc31f7f12497b5ff
  Author: Kai Luo <lkail at cn.ibm.com>
  Date:   2024-01-10 (Wed, 10 Jan 2024)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCInstrInfo.td
    M llvm/test/CodeGen/PowerPC/intrinsic-trap.ll

  Log Message:
  -----------
  [PowerPC] Make verifier happy when lowering `llvm.trap` (#77266)

`llvm.trap` is lowered to `PPC::TRAP` and `PPC::TRAP` is set as
terminator. Verifier complains about terminator should not lie in the
middle of an MBB. See #77095.

Fix it by removing `isTerminator` and `isBarrier` and then set `isTrap`
which was introduced by https://reviews.llvm.org/D48836# and is being
used by X86 and AArch64.

`PPC::TRAP` is not a hardware memory barrier and `llvm.trap` doesn't
indicate a memory barrier either.