[all-commits] [llvm/llvm-project] dbea53: [DWARFLinker] Support MD5 checksums in the line ta...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Mon Jan 8 11:49:30 PST 2024
Branch: refs/heads/users/vitalybuka/spr/msan-unwind-stack-before-fatal-reports
Home: https://github.com/llvm/llvm-project
Commit: dbea538c4391caa8a369c0ccf720367f042185b1
https://github.com/llvm/llvm-project/commit/dbea538c4391caa8a369c0ccf720367f042185b1
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-05 (Fri, 05 Jan 2024)
Changed paths:
M llvm/lib/DWARFLinker/DWARFStreamer.cpp
M llvm/lib/DWARFLinkerParallel/DebugLineSectionEmitter.h
M llvm/lib/DWARFLinkerParallel/OutputSections.cpp
M llvm/lib/DWARFLinkerParallel/OutputSections.h
M llvm/test/tools/dsymutil/ARM/dwarf5-dwarf4-combination-macho.test
M llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
Log Message:
-----------
[DWARFLinker] Support MD5 checksums in the line table (#77151)
Add support to the DWARF linkers for emitting DWARF 5 MD5 checksum in
the line table.
Commit: 2873060f3cfbd92dcff8d1037a08e9fb60f7882e
https://github.com/llvm/llvm-project/commit/2873060f3cfbd92dcff8d1037a08e9fb60f7882e
Author: Micah Weston <micahsweston at gmail.com>
Date: 2024-01-05 (Fri, 05 Jan 2024)
Changed paths:
M llvm/include/llvm/Object/ELFTypes.h
M llvm/lib/Object/ELF.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP] Fixes two bugs in decoding of PGOAnalyses in BBAddrMap. (#77139)
We had specified that `readBBAddrMap` will always keep PGOAnalyses and
BBAddrMaps the same length on success.
https://github.com/llvm/llvm-project/blob/365fbbfbcfefb8766f7716109b9c3767b58e6058/llvm/include/llvm/Object/ELFObjectFile.h#L116-L117
It turns out that this is not currently the case when no analyses exist
in a function. No test had caught it.
We also should not append PGOBBEntries when there is no BBFreq or
BrProb.
This patch adds:
* tests that PGOAnalyses and BBAddrMaps are same length even when no
analyses are enabled
* fixes decode so that PGOAnalyses and BBAddrMaps are same length
* updates test to not emit unnecessary PGOBBEntries
* fixes decode to not emit PGOBBEntries when unnecessary
Commit: 1637c0792550f70e4b2ef42b3d08aa91dd27f4a9
https://github.com/llvm/llvm-project/commit/1637c0792550f70e4b2ef42b3d08aa91dd27f4a9
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
M openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h
Log Message:
-----------
[openmp][amdgpu] Add DynamicLdsSize to AMDGPUImplicitArgsTy (#65325)
#65273 "hidden_dynamic_lds_size" argument will be added in the reserved
section at offset 120 of the implicit argument layout
Add DynamicLdsSize to AMDGPUImplicitArgsTy struct at offset 120 and fill
the dynamic LDS size before kernel launch.
Commit: ba3ef331b4568b5996172076572581e68c2d3c0c
https://github.com/llvm/llvm-project/commit/ba3ef331b4568b5996172076572581e68c2d3c0c
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2024-01-05 (Fri, 05 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
Log Message:
-----------
[RISCV][GlobalISel] Zbkb support for G_BSWAP (#77050)
This instructions is legal in the presence of Zbkb extension.
Commit: a5902a4d2425ac083f1530719e35b5c562cb1e60
https://github.com/llvm/llvm-project/commit/a5902a4d2425ac083f1530719e35b5c562cb1e60
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/X86.h
A llvm/lib/Target/X86/X86CompressEVEX.cpp
R llvm/lib/Target/X86/X86EvexToVex.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/test/CodeGen/X86/O0-pipeline.ll
M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/utils/TableGen/CMakeLists.txt
A llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
R llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
Log Message:
-----------
[X86][NFC] Rename variables/passes for EVEX compression optimization
RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031
APX introduces EGPR, NDD and NF instructions. In addition to compressing
EVEX encoded AVX512 instructions into VEX encoding, we also have several
more possible optimizations.
a. Promoted instruction (EVEX space) -> pre-promotion instruction (legacy space)
b. NDD (EVEX space) -> non-NDD (legacy space)
c. NF_ND (EVEX space) -> NF (EVEX space)
The first two types of compression can usually reduce code size, while
the third type of compression can help hardware decode although the
instruction length remains unchanged.
So we do the renaming for the upcoming APX optimizations.
BTW, I clang-format the code in X86CompressEVEX.cpp,
X86CompressEVEXTablesEmitter.cpp.
This patch also extracts the NFC in #77065 into a separate commit.
Commit: 241e4c7466b877265e1645ca4709fe666c95c6c4
https://github.com/llvm/llvm-project/commit/241e4c7466b877265e1645ca4709fe666c95c6c4
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Fixup for #77008 (`orc::SymbolMap`)
Commit: 16094cb629159ee0896e2ca1facc15118b229665
https://github.com/llvm/llvm-project/commit/16094cb629159ee0896e2ca1facc15118b229665
Author: hev <wangrui at loongson.cn>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
A llvm/test/CodeGen/LoongArch/global-variable-code-model.ll
Log Message:
-----------
[llvm][LoongArch] Support per-global code model attribute for LoongArch (#72079)
This patch gets the code model from global variable attribute if it has,
otherwise the target's will be used.
---------
Signed-off-by: WANG Rui <wangrui at loongson.cn>
Commit: 602c8fa2d8da6562e4f36df3bd63c26a4c7461e7
https://github.com/llvm/llvm-project/commit/602c8fa2d8da6562e4f36df3bd63c26a4c7461e7
Author: Craig Hesling <craig at hesling.com>
Date: 2024-01-05 (Fri, 05 Jan 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[GitHub] Fix slow sccache install on macOS by upgrading macOS version (#77165)
The "Setup ccache" step on macOS-11 builds takes between 15 to 20 mins,
whereas this step takes a less than 10 seconds on other runners. The
bulk of this time is spent at the "Install sccache" step, where brew
emits warnings like "Warning: You are using macOS 11." and "We (and
Apple) do not provide support for this old version...".
Bumping the version of macOS greatly decreases this cache setup time to
about 20 seconds. Furthermore, it seems like it is speeding up general
build times, too.
It appears that
https://github.com/actions/virtual-environments/issues/5900 has been
resolved or obsoleted, so I do not believe
we need to lock macOS to 11 anymore.
Commit: cf02e6e71064ba2ce36c354e3bd6b2d57de29d85
https://github.com/llvm/llvm-project/commit/cf02e6e71064ba2ce36c354e3bd6b2d57de29d85
Author: Craig Hesling <craig at hesling.com>
Date: 2024-01-05 (Fri, 05 Jan 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[GitHub] Remove redundant cache key prefix (#76914)
Remove the redundant sccache cache key prefix.
This prefix is already added by the ccache action, which results in
cache keys like "sccache-sccache-ubuntu-...".
See the following source lines as proof:
https://github.com/hendrikmuhs/ccache-action/blob/2a51777f6f64b7b7bea213601acba8f5f4fdbe03/src/restore.ts#L22-L23
Commit: 376baeb2d535826eb2d8158c4147e37cda493f35
https://github.com/llvm/llvm-project/commit/376baeb2d535826eb2d8158c4147e37cda493f35
Author: Craig Hesling <craig at hesling.com>
Date: 2024-01-05 (Fri, 05 Jan 2024)
Changed paths:
A .github/workflows/libclang-python-tests.yml
Log Message:
-----------
[GitHub] Add basic CI for libclang Python binding unit tests (#76784)
This is important to aid development of Python type annotations in the
libclang binding.
See https://github.com/llvm/llvm-project/issues/76664 for more details.
* Run on all pull requests and direct pushes.
* This makes use of the existing llvm-project-tests.yml recipe, which
will preload ccache from previous runs.
* Building libclang currently takes about 9mins when ccache is warm and
about an 1hr 20mins if it is cold using the standard GitHub ubuntu
runner.
* In the future, this could be broken into the following discrete steps
for clarity:
1. Build libclang dependency.
ninja -C build libclang
2. Run Python unit tests.
ninja -C build check-clang-python
* Followup changes will bring testing on older python versions and
static type checking.
Issue https://github.com/llvm/llvm-project/issues/76601.
Commit: 80dbf601d1815ff90b5aee18f426da964920dbe7
https://github.com/llvm/llvm-project/commit/80dbf601d1815ff90b5aee18f426da964920dbe7
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFormats.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
A llvm/utils/TableGen/X86ManualCompressEVEXTables.def
Log Message:
-----------
[X86][NFC] Remove EVEX2VEXOverride/NotEVEX2VEXConvertible
Remove these two classes and put all the entries in X86 EVEX compression tables
that need special handling in .def file.
PR #77065 tries to add entries that need special handling for APX in
.def file. Compared to setting fields in td files, that method looks
cleaner. This patch is to unify the addition of manual entries.
Commit: 04a7ec610ee1ad869e402c327984cb649be86f3c
https://github.com/llvm/llvm-project/commit/04a7ec610ee1ad869e402c327984cb649be86f3c
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFormats.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
M llvm/utils/TableGen/X86FoldTablesEmitter.cpp
M llvm/utils/TableGen/X86ManualCompressEVEXTables.def
Log Message:
-----------
[X86][NFC] Remove VEX_W1X after 80dbf60
Commit: b2246cf73e10c38aefffd923e4b53a1975f45909
https://github.com/llvm/llvm-project/commit/b2246cf73e10c38aefffd923e4b53a1975f45909
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Bazel port for a5902a4d2425ac083f1530719e35b5c562cb1e60
Commit: ab073cbccb6e79d8b65a286e8948bc1f07c7c09b
https://github.com/llvm/llvm-project/commit/ab073cbccb6e79d8b65a286e8948bc1f07c7c09b
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/test/tools/llvm-dwarfdump/AArch64/verify-no-file.yaml
Log Message:
-----------
Add requires darwin to verify-no-file.yaml (#77188)
Commit: 5b33cff39753c790ecc6847435664592abe40415
https://github.com/llvm/llvm-project/commit/5b33cff39753c790ecc6847435664592abe40415
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/test/Conversion/SCFToGPU/no_blocks_no_threads.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/outlining.mlir
Log Message:
-----------
[mlir][gpu] Add Support for Cluster of Thread Blocks in `gpu.launch` (#76924)
Commit: 1687555572ee4fb435da400dde02e7a1e60b742c
https://github.com/llvm/llvm-project/commit/1687555572ee4fb435da400dde02e7a1e60b742c
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
Log Message:
-----------
[GlobalIsel] Combine select of binops (#76763)
Commit: 0abf3a93a3088140c0585672c8b852e5db93a302
https://github.com/llvm/llvm-project/commit/0abf3a93a3088140c0585672c8b852e5db93a302
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
Log Message:
-----------
[X86][NFC] Use single table for EVEX compression
This patch is to address my review comments in #77065 to simplify the
implemention of EVEX2Legacy compression.
Commit: bd0dc357af453f03770c5d43c66ee5a3584abdca
https://github.com/llvm/llvm-project/commit/bd0dc357af453f03770c5d43c66ee5a3584abdca
Author: Abhinav271828 <71174780+Abhinav271828 at users.noreply.github.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
A mlir/include/mlir/Analysis/Presburger/GeneratingFunction.h
R mlir/lib/Analysis/Presburger/GeneratingFunction.h
M mlir/unittests/Analysis/Presburger/CMakeLists.txt
A mlir/unittests/Analysis/Presburger/GeneratingFunctionTest.cpp
M mlir/unittests/Analysis/Presburger/Utils.h
Log Message:
-----------
[MLIR][Presburger] Shift GeneratingFunction.h to includes (#77114)
We shift the GeneratingFunction.h header file to the include/ directory
and wrap it in a `detail` namespace.
Commit: d08482924efe8b2c44913583af7b8f60a29975d1
https://github.com/llvm/llvm-project/commit/d08482924efe8b2c44913583af7b8f60a29975d1
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp
Log Message:
-----------
[clang-tidy] fix false positive in cppcoreguidelines-missing-std-forward (#77056)
Parameter variable which is forwarded in lambda capture list or in body
by reference is reasonable and current version of this check produces
false positive on these cases. This patch try to fix the
[issue](https://github.com/llvm/llvm-project/issues/68105)
Co-authored-by: huqizhi <836744285 at qq.com>
Commit: 3fb0d8dc808cb7f315670d76109edc9c57cb3d90
https://github.com/llvm/llvm-project/commit/3fb0d8dc808cb7f315670d76109edc9c57cb3d90
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
Log Message:
-----------
Recommit "[VPlan] Mark Select VPInstructions as not having sideeffects."
With #70253 landed, selects for reduction results are explicitly used by
ComputeReductionResult and Selects can be marked as not having
side-effects again.
This reverts the revert commit 173032902c960d4d0d67b521d8c149553d8e8ba3.
Commit: 4b9bbd38686af3dbffd45b360bd5af629426bdbc
https://github.com/llvm/llvm-project/commit/4b9bbd38686af3dbffd45b360bd5af629426bdbc
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
Log Message:
-----------
[X86][NFC] Refine code in X86CompressEVEXTablesEmitter.cpp
1. Simplify getValueFromBitsInit about cast and return type
2. Remove out-of-date comments and allow memory ops in function
object `IsMatch` so that we can reuse it for EVEX2Legacy compression.
This patch is to extract NFC in #77065 into a separate commit.
Commit: 8bbf100799a97f8342bf1a8409c6fb48f03e837f
https://github.com/llvm/llvm-project/commit/8bbf100799a97f8342bf1a8409c6fb48f03e837f
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
Log Message:
-----------
[X86][NFC] Remove dead code for "_REV" instructions
Those "_REV" instructions should not appear before encoding
optimization, while macro fusion and flag-copy lowering are before
encoding optimization.
Commit: 0c7d46a7fd5b7956e285d385a6945153d6a06eb0
https://github.com/llvm/llvm-project/commit/0c7d46a7fd5b7956e285d385a6945153d6a06eb0
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
Log Message:
-----------
[Clang] Correctly construct template arguments for template template parameters (#76811)
This fixes the bug introduced by
https://github.com/llvm/llvm-project/commit/6db007a0654ed7a6ed5c3aa3b61a937c19a6bc6b.
We construct placeholder template arguments for template-template
parameters to avoid mismatching argument substitution since they have
different depths with their corresponding template arguments. In this
case,
```cpp
template <template <Concept C> class T> void foo(T<int>);
```
T lies at the depth 0, and C lies at 1. The corresponding argument, of
which there is exactly one, int, is at depth 0. If we consider the
argument as the outermost one, then we would end up substituting 'int'
into the wrong parameter T.
We used to perform such placeholder construction during the context
walk-up. In the previous patch, we slipped through that inadvertently
because we would walk up to the parent, which is precisely a FileContext
for template-template parameters, after adding innermost arguments.
Besides, this patch moves the sanity check up to the context switch.
That way, we avoid dereferencing null pointers if ND is unspecified.
Closes https://github.com/llvm/llvm-project/issues/57410.
Closes https://github.com/llvm/llvm-project/issues/76604. (The case is
slightly different than that in #57410. We should *not* assume the
surrounding context to be a file-scope one.)
Commit: 61bb3d499a234f20b74e70a37a68c0c7d47eb5dc
https://github.com/llvm/llvm-project/commit/61bb3d499a234f20b74e70a37a68c0c7d47eb5dc
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
Log Message:
-----------
[X86][NFC] Avoid uselss iterations when emitting EVEX compression table
BTW, we relax the condition for EVEX compression from
ST.hasAVX512() to ST.hasEGPR() || ST.hasAVX512(). It does not have any
effect now b/c no APX instruction is in the EVEX compression table so
far.
This patch is to extract NFC in #77065 into a separate commit.
Commit: a085402ef54379758e6c996dbaedfcb92ad222b5
https://github.com/llvm/llvm-project/commit/a085402ef54379758e6c996dbaedfcb92ad222b5
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
Log Message:
-----------
Revert "[GlobalIsel] Combine select of binops (#76763)"
This reverts commit 1687555572ee4fb435da400dde02e7a1e60b742c.
Commit: b5de136ef3fd63c6a6aabaea16792e47be1eeeff
https://github.com/llvm/llvm-project/commit/b5de136ef3fd63c6a6aabaea16792e47be1eeeff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
[RISCV] Refactor subreg indices. (#77173)
-Rename sub_32_hi to sub_gpr_odd
-Add dedicated sub_gpr_even.
-Rename sub_32 and sub_16 to sub_fpr32 and sub_fpr16.
-Remove start offset from sub_gpr_odd. AArch64 doesn't use non-zero offset for GPR
tuples so I don't think we need to.
This is preparation for a RV64 GPRPair for Zacas.
Commit: 747d8fb01c2417546ebaa774874ff8c3005e058a
https://github.com/llvm/llvm-project/commit/747d8fb01c2417546ebaa774874ff8c3005e058a
Author: Kohei Yamaguchi <fix7211 at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.h
M mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir
M mlir/test/Dialect/SPIRV/IR/cast-ops.mlir
M mlir/test/Dialect/SPIRV/IR/function-decorations.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Target/SPIRV/cast-ops.mlir
M mlir/test/Target/SPIRV/function-decorations.mlir
Log Message:
-----------
[mlir][spirv] Support alias/restrict function argument decorations (#76353)
Closes #76106
---------
Co-authored-by: Lei Zhang <antiagainst at gmail.com>
Commit: 6e1ecd100d7663a91135b1cf6c4a603681b7385b
https://github.com/llvm/llvm-project/commit/6e1ecd100d7663a91135b1cf6c4a603681b7385b
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
Log Message:
-----------
[gn build] Manually port ba3ef331
Commit: 83be8a74001904a63ed0cffa0cecc43649a7bb29
https://github.com/llvm/llvm-project/commit/83be8a74001904a63ed0cffa0cecc43649a7bb29
Author: Maksim Levental <maksim.levental at gmail.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M mlir/python/mlir/ir.py
M mlir/test/python/dialects/memref.py
Log Message:
-----------
[mlir][python] add MemRefTypeAttr attr builder (#76371)
Commit: 2af0695b875911144ed1f7b4e5679be500b86a77
https://github.com/llvm/llvm-project/commit/2af0695b875911144ed1f7b4e5679be500b86a77
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/docs/LangRef.rst
Log Message:
-----------
[docs] Small spelling fix ("if <...>`than` -> if <...> `then`") (#77215)
Commit: 90e7578a56704eff2143beb8fbe99e05b0a3bb24
https://github.com/llvm/llvm-project/commit/90e7578a56704eff2143beb8fbe99e05b0a3bb24
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll
Log Message:
-----------
[test] Test StackSafetyAnalysis handles MemIntrinsic even in the presence of __asan_memcpy
Commit: 0ebe97115dc79482cd9fa6a4bd31f9faa259dca0
https://github.com/llvm/llvm-project/commit/0ebe97115dc79482cd9fa6a4bd31f9faa259dca0
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Log Message:
-----------
Revert "[RISCV] Refactor subreg indices. (#77173)"
This reverts commit b5de136ef3fd63c6a6aabaea16792e47be1eeeff.
Based on post commit feedback, I need to some other work before
this makes sense.
Commit: c63febb1025564b078a5c8e52e6df638e8a1d808
https://github.com/llvm/llvm-project/commit/c63febb1025564b078a5c8e52e6df638e8a1d808
Author: Alex Beloi <alexbeloi at users.noreply.github.com>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
M mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
M mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
M mlir/test/Conversion/MemRefToSPIRV/bitwidth-emulation.mlir
M mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
M mlir/test/Dialect/SPIRV/IR/availability.mlir
M mlir/test/Dialect/SPIRV/IR/target-env.mlir
M mlir/test/Dialect/SPIRV/Transforms/inlining.mlir
M mlir/test/Target/SPIRV/atomic-ops.mlir
M mlir/test/Target/SPIRV/debug.mlir
Log Message:
-----------
[mlir][spirv] Use assemblyFormat to define atomic op assembly (#76323)
see #73359
Declarative assemblyFormat ODS is more concise and requires less
boilerplate than filling out CPP interfaces.
Changes:
* updates the Ops defined in `SPIRVAtomicOps.td` to use assemblyFormat.
* Removes print/parse from`AtomcOps.cpp` which is now generated by
assemblyFormat
* Adds `Trait` to verify that a pointer operand `foo`'s pointee type
matches operand `bar`'s type
* * Updates error message expected in tests from new Trait
* Updates tests to updated format (largely using <operand> in place of
"operand")
Commit: 5dfcb3e5d1d16bb4f8fce52b3c089119ed977e7f
https://github.com/llvm/llvm-project/commit/5dfcb3e5d1d16bb4f8fce52b3c089119ed977e7f
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-06 (Sat, 06 Jan 2024)
Changed paths:
M llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll
M llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll
M llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
Log Message:
-----------
[asan,test] Improve tests to ensure instrumentation even in the presence of StackSafetyAnalysis
Commit: 274f8332b9d1d460d38516f2c685692a46a93c7a
https://github.com/llvm/llvm-project/commit/274f8332b9d1d460d38516f2c685692a46a93c7a
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Log Message:
-----------
[RISCV] Don't attempt PRE if available info is SEW/LMUL ratio only (#77063)
Commit: 780a5116ba68ec8c53b65008b3407479478b2d5e
https://github.com/llvm/llvm-project/commit/780a5116ba68ec8c53b65008b3407479478b2d5e
Author: David Green <david.green at arm.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
Log Message:
-----------
[AArch64] Fix condition for combining UADDV and Add. (#76809)
This should have been checking that the transform was valid, but used
incorrect conditions letting through invalid combinations of lo/hi
extracts.
Hopefully fixes #76769
Commit: c82c54a1ef89ebd4903adfd977dabd34718a136e
https://github.com/llvm/llvm-project/commit/c82c54a1ef89ebd4903adfd977dabd34718a136e
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[Clang][NFC] Fix trailing whitespace in ReleaseNotes.rst
Commit: 4c8dbb68138959477d9fccbae3669663260dfe31
https://github.com/llvm/llvm-project/commit/4c8dbb68138959477d9fccbae3669663260dfe31
Author: Abhinav271828 <71174780+Abhinav271828 at users.noreply.github.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
A mlir/include/mlir/Analysis/Presburger/Barvinok.h
A mlir/lib/Analysis/Presburger/Barvinok.cpp
M mlir/lib/Analysis/Presburger/CMakeLists.txt
A mlir/unittests/Analysis/Presburger/BarvinokTest.cpp
M mlir/unittests/Analysis/Presburger/CMakeLists.txt
Log Message:
-----------
[MLIR][Presburger] Definitions for basic functions related to cones (#76650)
We add some basic type aliases and function definitions relating to
cones for Barvinok's algorithm.
These include functions to get the dual of a cone and find its index.
Commit: 2835be82db2037367154bc3226473947abbf661f
https://github.com/llvm/llvm-project/commit/2835be82db2037367154bc3226473947abbf661f
Author: Abhinav271828 <71174780+Abhinav271828 at users.noreply.github.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/GeneratingFunction.h
M mlir/unittests/Analysis/Presburger/GeneratingFunctionTest.cpp
Log Message:
-----------
[MLIR][Presburger] Fix ParamPoint to be column-wise instead of row-wise (#77232)
The ParamPoint datatype has each column representing an affine function.
The code for generating functions is modified to reflect this.
Commit: 3eb9fd8ac8bb7524b45912115dc212b7e80be588
https://github.com/llvm/llvm-project/commit/3eb9fd8ac8bb7524b45912115dc212b7e80be588
Author: Bharathi Ramana Joshi <joshibharathiramana at gmail.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
Log Message:
-----------
[MLIR][Presburger] Implement IntegerRelation::mergeAndAlignSymbols (#76736)
Commit: 0903d992cc961281a0bffc8704796f27f8c2e696
https://github.com/llvm/llvm-project/commit/0903d992cc961281a0bffc8704796f27f8c2e696
Author: Bill Wendling <morbo at google.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemoryBuiltins.h
Log Message:
-----------
[NFC][ObjectSizeOffset] Add template stuff for Visual Studio
Visual Studio needs the class template stuff.
C:\llvm\include\llvm/Analysis/MemoryBuiltins.h(217): error C2990: 'llvm::SizeOffsetType': non-class template has already been declared as a class template
C:\llvm\include\llvm/Analysis/MemoryBuiltins.h(193): note: see declaration of 'llvm::SizeOffsetType'
Commit: fd1c156e5d6584684ce58c0536dca96cedcc41f0
https://github.com/llvm/llvm-project/commit/fd1c156e5d6584684ce58c0536dca96cedcc41f0
Author: Bill Wendling <morbo at google.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemoryBuiltins.h
Log Message:
-----------
Revert "[NFC][ObjectSizeOffset] Add template stuff for Visual Studio"
This reverts commit 0903d992cc961281a0bffc8704796f27f8c2e696.
This is causing all non-Visual Studio builds fail.
Commit: 2eb7a82af3b66f9448f9d2843b438fa8ec4ff53f
https://github.com/llvm/llvm-project/commit/2eb7a82af3b66f9448f9d2843b438fa8ec4ff53f
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/icmp.ll
Log Message:
-----------
[InstCombine] Relax the one-use constraints for `icmp pred (binop X, Z), (binop Y, Z)` (#76384)
This patch relaxes the one-use constraints for `icmp pred (binop X, Z),
(binop Y, Z)`. It will enable more optimizations with pointer
arithmetic.
One example in `boost::match_results::set_size`:
```
declare void @use(i64)
define i1 @src(ptr %a1, ptr %a2, ptr %add.ptr.i66, i64 %sub.ptr.rhs.cast.i) {
%sub.ptr.lhs.cast.i = ptrtoint ptr %a1 to i64
%sub.ptr.rhs.cast.i = ptrtoint ptr %a2 to i64
%sub.ptr.sub.i = sub i64 %sub.ptr.lhs.cast.i, %sub.ptr.rhs.cast.i
%sub.ptr.div.i = sdiv exact i64 %sub.ptr.sub.i, 24
call void @use(i64 %sub.ptr.div.i)
%sub.ptr.lhs.cast.i.i = ptrtoint ptr %add.ptr.i66 to i64
%sub.ptr.sub.i.i = sub i64 %sub.ptr.lhs.cast.i.i, %sub.ptr.rhs.cast.i
%sub.ptr.div.i.i = sdiv exact i64 %sub.ptr.sub.i.i, 24
%cmp.i.not.i.i = icmp eq i64 %sub.ptr.div.i.i, %sub.ptr.div.i
ret i1 %cmp.i.not.i.i
}
define i1 @tgt(ptr %a1, ptr %a2, ptr %add.ptr.i66, i64 %sub.ptr.rhs.cast.i) {
%sub.ptr.lhs.cast.i = ptrtoint ptr %a1 to i64
%sub.ptr.rhs.cast.i = ptrtoint ptr %a2 to i64
%sub.ptr.sub.i = sub i64 %sub.ptr.lhs.cast.i, %sub.ptr.rhs.cast.i
%sub.ptr.div.i = sdiv exact i64 %sub.ptr.sub.i, 24
call void @use(i64 %sub.ptr.div.i)
%cmp.i.not.i.i = icmp eq i64 %sub.ptr.sub.i.i, %sub.ptr.sub.i
ret i1 %cmp.i.not.i.i
}
```
Commit: dd450f08cfeb9da372cbe459058bc9ae9425f862
https://github.com/llvm/llvm-project/commit/dd450f08cfeb9da372cbe459058bc9ae9425f862
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/BufferUtils.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
M mlir/lib/Dialect/Bufferization/Transforms/BufferOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
Log Message:
-----------
[mlir][Interfaces][NFC] Move region loop detection to `RegionBranchOpInterface` (#77090)
`BufferPlacementTransformationBase::isLoop` checks if there a loop in
the region branching graph of an operation. This algorithm is similar to
`isRegionReachable` in the `RegionBranchOpInterface`. To avoid duplicate
code, `isRegionReachable` is generalized, so that it can be used to
detect region loops. A helper function
`RegionBranchOpInterface::hasLoop` is added.
This change also turns a recursive implementation into an iterative one,
which is the preferred implementation strategy in LLVM.
Also move the `isLoop` to `BufferOptimizations.cpp`, so that we can
gradually retire `BufferPlacementTransformationBase`. (This is so that
proper error handling can be added to `BufferViewFlowAnalysis`.)
Commit: 752df2bc0b606127efea80023b0dfd8a7a36bf8c
https://github.com/llvm/llvm-project/commit/752df2bc0b606127efea80023b0dfd8a7a36bf8c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Transforms/BufferUtils.h
M mlir/include/mlir/IR/Dominance.h
Log Message:
-----------
[mlir][IR] `DominanceInfo`: Add function to query dominator of a range of block (#77098)
Also improve the implementation of `findCommonDominator` (skip duplicate
blocks) and extract it from `BufferPlacementTransformationBase` (so that
`BufferPlacementTransformationBase` can be retired eventually).
Commit: 1f9c2ddd8c1c5ff013c1f3b5570a0af0657311a8
https://github.com/llvm/llvm-project/commit/1f9c2ddd8c1c5ff013c1f3b5570a0af0657311a8
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp
Log Message:
-----------
[libc++][test] Improves suspurious clang diagnostics. (#77234)
As suggested by @philnik777 this is a better fix than
02a33b72fd21cdbf476d6bda72faa462e073e510
Fixes: https://github.com/llvm/llvm-project/issues/77123
Commit: 249d2ccb1d8475d3ff4ead9566a83fc0adf476db
https://github.com/llvm/llvm-project/commit/249d2ccb1d8475d3ff4ead9566a83fc0adf476db
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
Log Message:
-----------
[LV] Add test showing overly aggressive dropping of inbounds.
As %B.gep.0 executes unconditionally in the latch, inbounds could
be preserved in the vector version.
https://alive2.llvm.org/ce/z/XWbMuD
Commit: 18ec3304a9e4aed25d998180728faaf02236205d
https://github.com/llvm/llvm-project/commit/18ec3304a9e4aed25d998180728faaf02236205d
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
Log Message:
-----------
[VPlan] Manage InBounds via VPRecipeWithIRFlags for VectorPtrRecipe.
As suggested as follow-up in
https://github.com/llvm/llvm-project/pull/72164, manage inbounds via
VPRecipeWithIRFlags.
Note that in some cases we can now preserve inbounds in a few more
cases.
Commit: e497f689236dc2f14f08f09e1af8c2b10820952a
https://github.com/llvm/llvm-project/commit/e497f689236dc2f14f08f09e1af8c2b10820952a
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M libcxx/include/tuple
Log Message:
-----------
[NFC][libc++] Formats tuple.
The fix used macros that confuses clang-format. This is formatted with
clang-format and then excluded from formatting.
Commit: 3e498b3db5bdd6b0e8cbebb1d8ac88a59b4eef7a
https://github.com/llvm/llvm-project/commit/3e498b3db5bdd6b0e8cbebb1d8ac88a59b4eef7a
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/18.rst
Log Message:
-----------
[libc++][doc] Minor release notes style fixes.
Commit: 8f76f1816ea63b7cc28e150ba319ffbfe6351f9e
https://github.com/llvm/llvm-project/commit/8f76f1816ea63b7cc28e150ba319ffbfe6351f9e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M clang/test/Driver/linker-wrapper-image.c
Log Message:
-----------
[OpenMP][Obvious] Fix test failing on BE architectures
Summary:
This accidentally included a byte past the magic, which was out of order
on big endian architectures.
Commit: b306a9c9986f254d0aff5eb892da9359e2588f54
https://github.com/llvm/llvm-project/commit/b306a9c9986f254d0aff5eb892da9359e2588f54
Author: natanelh-mobileye <155897558+natanelh-mobileye at users.noreply.github.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
Log Message:
-----------
[PatternMatch] Fix typo in comment (NFC) (#77240)
Tiny spelling mistake fixup. please review the two lines of code below
to see the correctness of this PR.
Commit: 535d8e8b92e3f8cf4107d9431012310c9a72c8d3
https://github.com/llvm/llvm-project/commit/535d8e8b92e3f8cf4107d9431012310c9a72c8d3
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SwitchLoweringUtils.cpp
Log Message:
-----------
NFC: Extract switch lowering binary tree splitting code from DAG into SwitchLoweringUtils.
This will help re-use this code with the upcoming GlobalISel implementation of
this optimization.
Commit: 92e243173c09fc78c25814a7d7e392971034f5be
https://github.com/llvm/llvm-project/commit/92e243173c09fc78c25814a7d7e392971034f5be
Author: Hristo Hristov <hristo.goshev.hristov at gmail.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/18.rst
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/fstream
M libcxx/include/version
M libcxx/src/CMakeLists.txt
A libcxx/src/fstream.cpp
A libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/fstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/fstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/native_handle_assert_test_helpers.h
A libcxx/test/std/input.output/file.streams/fstreams/native_handle_test_helpers.h
A libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream/types.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/types.h
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
Reapply "[libc++][streams] P1759R6: Native handles and file streams" (#77190)
Fixes build on Windows in C++26 mode.
Reverted in:
https://github.com/llvm/llvm-project/commit/40c07b559aa6ab4bac074c943967d3207bc07ae0
Original PR: https://github.com/llvm/llvm-project/pull/76632
---------
Co-authored-by: Zingam <zingam at outlook.com>
Commit: 38228d5efe18cbe45ea02ebb08b2d2a7e4b68560
https://github.com/llvm/llvm-project/commit/38228d5efe18cbe45ea02ebb08b2d2a7e4b68560
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/include/CMakeLists.txt
M libc/src/__support/StringUtil/CMakeLists.txt
Log Message:
-----------
[libc] Fix GPU tests not running after recent patches (#77248)
Summary:
A previous patch added a dependency on the stack protectors, this was
not built on the GPU targets so every test was disabled. It turns out
that disabled tests still get targets so we need to specifically check
if the it is in the target's set of entrypoints before we can use it.
Another patch, because the build-bot was down, snuck in that prevented
the new math tests from being run. The problem is that the `signal.h`
header requires target specific definitions but was being used
unconditionally. I have made changes that disable building this header
if the file is not defined in the config. This required disbaling the
signal_to_string utility, so that will simply be missing from targets
that don't define it.
Commit: fece9818abce9339e3a46ce174c662602e32d593
https://github.com/llvm/llvm-project/commit/fece9818abce9339e3a46ce174c662602e32d593
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M libc/include/CMakeLists.txt
Log Message:
-----------
[libc] Attempt to fix incorrect pathin on Linux builds
Commit: c5e35986d8064775182b03a7e1a7e02f1cf7e4a9
https://github.com/llvm/llvm-project/commit/c5e35986d8064775182b03a7e1a7e02f1cf7e4a9
Author: Nicholas Mosier <nh.mosier at gmail.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M lld/ELF/Arch/X86_64.cpp
M lld/test/ELF/x86-64-tls-pie.s
Log Message:
-----------
[lld][ELF][X86] Add missing X86_64_TPOFF64 case in switches (#77208)
Close #77201. When linking code with a R_X86_64_TPOFF64 relocation, LLD
exits with an 'unknown reloaction' error message due to two missing
cases in relocation switch statements. This patch adds in those cases so
that LLD successfully links code R_X86_64_TPOFF64 relocations.
Commit: eabaee0c59110d0e11b33a69db54ccda526b35fd
https://github.com/llvm/llvm-project/commit/eabaee0c59110d0e11b33a69db54ccda526b35fd
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/addrspacecast.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/analyze-branch.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-frem.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/byval.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-fcmp.ll
M llvm/test/CodeGen/RISCV/double-frem.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/emutls.ll
M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fli-licm.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-fcmp.ll
M llvm/test/CodeGen/RISCV/float-frem.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-mem.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fp16-promote.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/frame-info.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-frem.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/nest-register.ll
M llvm/test/CodeGen/RISCV/nomerge.ll
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rem.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64-large-stack.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/split-sp-adjust.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-protector-target.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tls-models.ll
M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
M llvm/test/MC/RISCV/function-call.s
M llvm/test/MC/RISCV/tail-call.s
Log Message:
-----------
[RISCV] Omit "@plt" in assembly output "call foo at plt" (#72467)
R_RISCV_CALL/R_RISCV_CALL_PLT distinction is not necessary and
R_RISCV_CALL has been deprecated. Since https://reviews.llvm.org/D132530
`call foo` assembles to R_RISCV_CALL_PLT. The `@plt` suffix is not
useful and can be removed now (matching AArch64 and PowerPC).
GNU assembler assembles `call foo` to RISCV_CALL_PLT since 2022-09
(70f35d72ef04cd23771875c1661c9975044a749c).
Without this patch, unconditionally changing MO_CALL to MO_PLT could
create `jump .L1 at plt, a0`, which is invalid in LLVM integrated assembler
and GNU assembler.
Commit: 360996ac5ad26714a6ddbee45730fbcfb7dc3eea
https://github.com/llvm/llvm-project/commit/360996ac5ad26714a6ddbee45730fbcfb7dc3eea
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/make-compressible.mir
M llvm/test/CodeGen/RISCV/mir-target-flags.ll
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/vector-abi.ll
Log Message:
-----------
[RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)
Since #72467, `@plt` in assembly output "call foo at plt" is omitted. We
can trivially merge MO_PLT and MO_CALL without any functional change to
assembly/relocatable file output.
Earlier architectures use different call relocation types whether a PLT
is potentially needed: R_386_PLT32/R_386_PC32, R_68K_PLT32/R_68K_PC32,
R_SPARC_WDISP30/R_SPARC_WPLT320. However, as the PLT property is
per-symbol instead of per-call-site and linkers can optimize out a PLT,
the distinction has been confusing.
Arm made good names R_ARM_CALL/R_AARCH64_CALL. Let's use MO_CALL instead
of MO_PLT.
As follow-ups, we can merge fixup_riscv_call/fixup_riscv_call_plt and
VK_RISCV_CALL/VK_RISCV_CALL_PLT.
Commit: 4ca1b5e094280ef1af40412e3cfcb62dc3cf15bc
https://github.com/llvm/llvm-project/commit/4ca1b5e094280ef1af40412e3cfcb62dc3cf15bc
Author: Martin Storsjö <martin at martin.st>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/test/Driver/mingw-sysroot.cpp
Log Message:
-----------
[clang] [MinGW] Don't look for a GCC in path if the install base has a proper mingw sysroot (#76949)
This fixes uses of the MSYS2 clang64 environment compilers, if another
set of GCC based compilers are available further back in PATH (which may
be explicitly added, or inherited unintentionally from other software
installed).
(The issue in the clang64 environment can be worked around somewhat by
installing *-gcc-compat packages which present aliases named
<triple>-gcc within the clang64 environment as well.)
This fixes https://github.com/msys2/MINGW-packages/issues/11495 and
https://github.com/msys2/MINGW-packages/issues/19279.
Commit: f8c5541f5a6b6e4806f9fb5ab191d4a7e60609c4
https://github.com/llvm/llvm-project/commit/f8c5541f5a6b6e4806f9fb5ab191d4a7e60609c4
Author: Bill Wendling <morbo at google.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/MemoryBuiltins.h
Log Message:
-----------
[NFC][ObjectSize] Make method public
Windows barfs on the 'friend class SizeOffsetType;' statement. Attempt
to fix by making the method called by the "friend" class public.
Commit: 0359acf0f5f04da184386c886d56ee45db7b7be0
https://github.com/llvm/llvm-project/commit/0359acf0f5f04da184386c886d56ee45db7b7be0
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
A lld/test/ELF/eh-frame-nonzero-offset-riscv.s
Log Message:
-----------
[ELF,test] Add eh-frame-nonzero-offset-riscv.s for #65966
I plan to define RISCV::relocateAllocate in a subsequent change.
Add a test to verify
`else if (auto *ehIn = dyn_cast<EhInputSection>(&sec)) secAddr += ehIn->getParent()->outSecOff;`
Commit: 60c4f82d3c4e9cfc337c360f489d830d0379b04d
https://github.com/llvm/llvm-project/commit/60c4f82d3c4e9cfc337c360f489d830d0379b04d
Author: Petr Hosek <phosek at google.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/test/Instrumentation/InstrProfiling/platform.ll
M llvm/test/Instrumentation/InstrProfiling/profiling.ll
Log Message:
-----------
[InstrProfiling] No runtime registration for ELF, COFF, Mach-O and XCOFF (#77225)
Whether runtime registration is needed is not dependent on the OS but
the file format. For ELF, COFF, Mach-O or XCOFF, we can always use the
linker support. This is important for baremetal platforms such as RTOS
and UEFI platforms where there is no OS but we still don't want to use
runtime registration and rely on linker support instead.
Commit: c7cae61b289fd12171a2da80a6e90b867ee1c4fc
https://github.com/llvm/llvm-project/commit/c7cae61b289fd12171a2da80a6e90b867ee1c4fc
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
Log Message:
-----------
[NFC] Remove trailing whitespace in `llvm/lib/Target/AMDGPU/VOP2Instructions.td`
Commit: d6aef863d83e5a352e78a0211a935a59efda0a0c
https://github.com/llvm/llvm-project/commit/d6aef863d83e5a352e78a0211a935a59efda0a0c
Author: Chen Zheng <czhengsz at cn.ibm.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
Log Message:
-----------
[PowerPC] make LR/LR8 CTR/CTR8 aliased (#76926)
fixes https://github.com/llvm/llvm-project/issues/47156
fixes https://github.com/llvm/llvm-project/issues/47155
Commit: 5034994134bbec92c1f1116c56008ac504f7d763
https://github.com/llvm/llvm-project/commit/5034994134bbec92c1f1116c56008ac504f7d763
Author: Haocong Lu <74847248+Luhaocong at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/AST/FormatString.cpp
M clang/test/Sema/attr-format.c
M clang/test/SemaCXX/attr-format.cpp
M clang/test/SemaCXX/format-strings-scanf.cpp
Log Message:
-----------
[Sema] Warning for _Float16 passed to format specifier '%f' (#74439)
According to https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2844.pdf,
default argument promotions for _FloatN types has been removed.
A warning is needed to notice user to promote _Float16 to double
explicitly, and then pass it to format specifier '%f', which is
consistent with GCC.
Fixes: https://github.com/llvm/llvm-project/issues/68538
Commit: 78550bef98347bccbf0e8e5fb66dc59718fc35ec
https://github.com/llvm/llvm-project/commit/78550bef98347bccbf0e8e5fb66dc59718fc35ec
Author: Petr Hosek <phosek at google.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
[CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain (#76849)
This contains compiler-rt builtins and llvm-libc for baremetal use.
Differential Revision: https://reviews.llvm.org/D155337
Commit: 225e2704af3c53bc0c4ee6bf92f32ace54d10fbc
https://github.com/llvm/llvm-project/commit/225e2704af3c53bc0c4ee6bf92f32ace54d10fbc
Author: Kai Luo <gluokai at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
A llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
Log Message:
-----------
[PowerPC] Precommit test for lowering llvm.trap on ppc64le. NFC.
Commit: b58a97d6aea12a30e2d1b01c6289abb2fd061f0b
https://github.com/llvm/llvm-project/commit/b58a97d6aea12a30e2d1b01c6289abb2fd061f0b
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
Log Message:
-----------
[RISCV][NFC] Move Zawrs/Zacas implementation to RISCVInstrInfoZa.td (#76940)
To keep the structure of TableGen files clear.
The definitions are simplified by the way.
Commit: a90ed3e8a4ea8c5238fd660bbac0371366afe3b5
https://github.com/llvm/llvm-project/commit/a90ed3e8a4ea8c5238fd660bbac0371366afe3b5
Author: Petr Hosek <phosek at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
Log Message:
-----------
Revert "[CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain (#76849)"
This reverts commit 78550bef98347bccbf0e8e5fb66dc59718fc35ec since
it broke the two stage build.
Commit: f22cde10e7cc711bba9f43d7529ea6c1394c5b48
https://github.com/llvm/llvm-project/commit/f22cde10e7cc711bba9f43d7529ea6c1394c5b48
Author: Ningning Shi(史宁宁) <shiningning at iscas.ac.cn>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/ARM/ARMLegalizerInfo.h
M llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
Log Message:
-----------
[GlobalISel][NFC]Delete the comments of XXLegalizerInfo (#76918)
Delete the LegalizerInfo comments of AArch64/AMD64/ARM/M68k/RISCV/x86,
they are copied from register bank.
Commit: ce944597e43ae4f77260d4683f8d6535947fb0a2
https://github.com/llvm/llvm-project/commit/ce944597e43ae4f77260d4683f8d6535947fb0a2
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
Log Message:
-----------
[gn] port 92e243173c09
Commit: 1dfb9498333a6c7c6ac012eb70dc593f5165a025
https://github.com/llvm/llvm-project/commit/1dfb9498333a6c7c6ac012eb70dc593f5165a025
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
R lld/test/ELF/linkerscript/overlay-reject.test
R lld/test/ELF/linkerscript/overlay-reject2.test
M lld/test/ELF/linkerscript/overlay.test
Log Message:
-----------
[ELF] Improve OVERLAY tests
Also test two issues:
* When the start address is `.`, subsequent sections don't share the
address of the first overlay section.
* When the first overlay section is empty and discardable, `p_paddr` is
incorrectly zero. This is because a discarded section has a zero
address, causing `prev->getLMA() + prev->size` where `prev` refers to
the first section to evaluate to zero.
Commit: 93c8468c6cd154efb8fae16a4025e116be8181c7
https://github.com/llvm/llvm-project/commit/93c8468c6cd154efb8fae16a4025e116be8181c7
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
Log Message:
-----------
[X86][NFC] Remove duplicate comments in X86CompressEVEX.cpp
Commit: 624b48789f6941d5f10c9ddf144e2bf72365fdd1
https://github.com/llvm/llvm-project/commit/624b48789f6941d5f10c9ddf144e2bf72365fdd1
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll
Log Message:
-----------
[AArch64][NFC] Pre-commit IR translator switch lowering test.
Commit: b3037ae1fc6d26459e37f813757ad30872eb2eee
https://github.com/llvm/llvm-project/commit/b3037ae1fc6d26459e37f813757ad30872eb2eee
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp
M flang/test/Transforms/debug-line-table-existing.fir
M flang/test/Transforms/debug-line-table-inc-file.fir
M flang/test/Transforms/debug-line-table.fir
M mlir/examples/toy/Ch6/toyc.cpp
M mlir/examples/toy/Ch7/toyc.cpp
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir
M mlir/test/Dialect/LLVMIR/call-location.mlir
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
M mlir/test/Dialect/LLVMIR/global.mlir
M mlir/test/Dialect/LLVMIR/invalid-call-location.mlir
M mlir/test/Dialect/LLVMIR/loop-metadata.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/loop-metadata.mlir
Log Message:
-----------
[MLIR][LLVM] Add distinct identifier to DICompileUnit attribute (#77070)
This commit adds a distinct attribute parameter to the DICompileUnit to
enable the modeling of distinctness. LLVM requires DICompileUnits to be
distinct and there are cases where one gets two equivalent compilation
units but LLVM still requires differentiates them. We observed such
cases for combinations of LTO and inline functions.
This patch also changes the DIScopeForLLVMFuncOp pass to a module pass,
to ensure that only one distinct DICompileUnit is created, instead of
one for each function.
Commit: 9b808a4beb8e6c8255b412fdd6f5a3e20cbcf270
https://github.com/llvm/llvm-project/commit/9b808a4beb8e6c8255b412fdd6f5a3e20cbcf270
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
A clang/test/Modules/explicit-specializations.cppm
Log Message:
-----------
[NFC] [Modules] Add a test case for selecting specializations with aliased template args
This a test for https://github.com/llvm/llvm-project/pull/76774. In the
review comments, we're concerning about the case that ODRHash may
produce the different hash values for semantical same template
arguments. For example, if the template argument in a specialization is
not qualified and the semantical same template argument in the instantiation
point is qualified, we should be able to select that template
specialization. And this patch tests this behavior: we should be able to select
the correct specialization with semantical same template arguments.
Commit: fe1364f1e7ac0c4d0f9a4b15189485782241190d
https://github.com/llvm/llvm-project/commit/fe1364f1e7ac0c4d0f9a4b15189485782241190d
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll
Log Message:
-----------
Update pre-committed test. Accidentally committed the wrong version, this one
properly demonstrates the upcoming change.
Commit: 9de81ce87d9f99850d427c9e0440440b5ef9ebbf
https://github.com/llvm/llvm-project/commit/9de81ce87d9f99850d427c9e0440440b5ef9ebbf
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-07 (Sun, 07 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll
Log Message:
-----------
NFC: Another pre-commit test change.
Commit: bae1fdea712fcd0b0ea525b115e661f92263f2e7
https://github.com/llvm/llvm-project/commit/bae1fdea712fcd0b0ea525b115e661f92263f2e7
Author: Christian Ulmann <christianulmann at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp
M flang/test/Transforms/debug-line-table-inc-file.fir
M flang/test/Transforms/debug-line-table.fir
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
Log Message:
-----------
[MLIR][LLVM] Add distinct identifier to the DISubprogram attribute (#77093)
This commit adds an optional distinct attribute parameter to the
DISubprogramAttr. This enables modeling of distinct subprograms, as
required for LLVM IR. This change is required to avoid accidential
uniquing of subprograms on functions that would lead to invalid LLVM IR
post export.
Commit: 7e54ae24d84bce4452ac4a28acb6568db52980fb
https://github.com/llvm/llvm-project/commit/7e54ae24d84bce4452ac4a28acb6568db52980fb
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp
M mlir/test/Dialect/LLVMIR/inlining.mlir
Log Message:
-----------
[mlir][llvm] Do not inline variadic functions (#77241)
This revision updates the llvm dialect inliner to explicitly disallow
the inlining of variadic functions. Already previously the inlining
failed if the number of function arguments did not match the number of
call arguments. After the change, inlining checks the function is not
variadic and it does not contain a va_start intrinsic.
Commit: c15e5836d49763e43736d13eb4b873e01dcc9ef0
https://github.com/llvm/llvm-project/commit/c15e5836d49763e43736d13eb4b873e01dcc9ef0
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/test/AST/Interp/arrays.cpp
Log Message:
-----------
[clang][Interp] Fix nullptr array dereferencing (#75798)
The attached test case would cause an assertion failure in Pointer.h
when operating on a null pointer.
Commit: 6343b4e48205fe5772f707b9023e8a57c95154a9
https://github.com/llvm/llvm-project/commit/6343b4e48205fe5772f707b9023e8a57c95154a9
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M mlir/include/mlir/ExecutionEngine/RunnerUtils.h
Log Message:
-----------
[mlir] Apply ClangTidy performance finding
- Use '\n' instead of std::endl;
https://clang.llvm.org/extra/clang-tidy/checks/performance/avoid-endl.html
Commit: ca20c99bb185838e5f275cf27fdcaccb17d7978d
https://github.com/llvm/llvm-project/commit/ca20c99bb185838e5f275cf27fdcaccb17d7978d
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll
Log Message:
-----------
[GlobalISel][IRTranslator] Port switch binary tree search optimization. (#77279)
This re-uses some code extracted earlier from SelectionDAG into
SwitchLoweringUtils
Much of the code is a straight port from SDAG's splitWorkItem(), with
minor changes needed for GISel.
Commit: 2642240de9b9004a431f4e601c055c8c135c9d39
https://github.com/llvm/llvm-project/commit/2642240de9b9004a431f4e601c055c8c135c9d39
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M mlir/include/mlir/ExecutionEngine/RunnerUtils.h
Log Message:
-----------
[mlir] Add explicit call to flush
ClangTidy performance suggested to use '\n' instead of std::endl, but it
seems the flushing behavior was intended here (tests started failing).
Commit: 3574b61013b341c96d5c9b7d2ca5480a398586b3
https://github.com/llvm/llvm-project/commit/3574b61013b341c96d5c9b7d2ca5480a398586b3
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Analysis/VFABIDemangling.cpp
M llvm/unittests/Analysis/VectorFunctionABITest.cpp
Log Message:
-----------
[VFABI] Reject demangled variants with unexpected number of params. (#76855)
When demangling a vector variant we are not checking that the number of
parameters is the same as that of the scalar function. This check is
hoisted out of getScalableECFromSignature() making the equvalent check
in the unittests obsolete.
Commit: 1c674666fa3bc0cf6d62d920bdddc846b8105d12
https://github.com/llvm/llvm-project/commit/1c674666fa3bc0cf6d62d920bdddc846b8105d12
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
M llvm/test/CodeGen/X86/invpcid-intrinsic.ll
M llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll
M llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll
M llvm/test/CodeGen/X86/sha.ll
M llvm/test/CodeGen/X86/x64-cet-intrinsics.ll
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
Log Message:
-----------
[X86] Support EVEX compression for EGPR (#77202)
Compress promoted instruction (EVEX) to pre-promotion instruction
(legacy/VEX) when R16-R31 is not used.
Alternative of #77065
Commit: 68a1583a8900fe13e33fe9ff6005f7a3e5b82c53
https://github.com/llvm/llvm-project/commit/68a1583a8900fe13e33fe9ff6005f7a3e5b82c53
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
Log Message:
-----------
[TLI] replace-with-veclib works with FRem Instruction. (#76166)
Updated SLEEF and ArmPL tests with Fixed-Width and Scalable cases for
frem. Those are mapped to fmod/fmodf.
Commit: acbb491ab23fd04e201b58195f78e04c5a647d47
https://github.com/llvm/llvm-project/commit/acbb491ab23fd04e201b58195f78e04c5a647d47
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libcxx/cmake/caches/Armv7M-picolibc.cmake
M libcxx/utils/qemu_baremetal.py
Log Message:
-----------
[libcxx] Require qemu-system-arm for armv7m builder (#77067)
And add a check in the python script that the binary given to `--qemu`
actually exists. Otherwise you get a generic Python error:
```
# .---command stderr------------
# | Traceback (most recent call last):
# | File "/home/david.spickett/modules-llvm-project/libcxx/utils/qemu_baremetal.py", line 70, in <module>
# | exit(main())
# | File "/home/david.spickett/modules-llvm-project/libcxx/utils/qemu_baremetal.py", line 66, in main
# | os.execvp(qemu_commandline[0], qemu_commandline)
# | File "/usr/lib/python3.8/os.py", line 568, in execvp
# | _execvpe(file, args)
# | File "/usr/lib/python3.8/os.py", line 610, in _execvpe
# | raise last_exc
# | File "/usr/lib/python3.8/os.py", line 601, in _execvpe
# | exec_func(fullname, *argrest)
# | FileNotFoundError: [Errno 2] No such file or directory
# `-----------------------------
# error: command failed with exit status: 1
```
When it tries to run the entire command later.
For the builder, it's only ever going to use qemu-system-arm so error at
config time if it's not there.
Commit: ed1632b72ec029256f3af60822dad54970a79577
https://github.com/llvm/llvm-project/commit/ed1632b72ec029256f3af60822dad54970a79577
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll
Log Message:
-----------
[ConstraintElim] Support signed induction variables (#77103)
When adding information for induction variables, add both unsigned and
signed constraints, with corresponding signed and unsigned
preconditions.
I believe the logic here is equally valid for signed/unsigned, we just
need to add preconditions of the same type.
Commit: 2c213c45046b78eac48809b013e7a80099607ebb
https://github.com/llvm/llvm-project/commit/2c213c45046b78eac48809b013e7a80099607ebb
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/test/Driver/riscv-rvv-vector-bits.c
Log Message:
-----------
[Clang] Fix reference to sve in rvv driver test comment. NFC
Commit: d02c7931d1be794a230943e300fec4172032e6a8
https://github.com/llvm/llvm-project/commit/d02c7931d1be794a230943e300fec4172032e6a8
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Analysis/MemorySSAUpdater.cpp
A llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll
Log Message:
-----------
[MSSA] Don't require clone creation to succeed (#76819)
Sometimes, we create a MemoryAccess for an instruction, which is later
simplified (e.g. via devirtualization) such that the new instruction has
no memory effects anymore.
If we later clone the instruction (e.g. during unswitching), then MSSA
will not create a MemoryAccess for the new instruction, triggering an
assert.
Disable the assertion (by passing CreationMustSucceed=false) and adjust
getDefiningAccessForClone() to work correctly in that case.
This PR implements the alternative suggestion by alinas from
https://github.com/llvm/llvm-project/pull/76142.
Commit: 442f67c8702a792a135d61765909b732827d6bf2
https://github.com/llvm/llvm-project/commit/442f67c8702a792a135d61765909b732827d6bf2
Author: Lu Haocong <haoconglu at qq.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
A clang/test/Sema/attr-format-Float16.c
M clang/test/Sema/attr-format.c
A clang/test/SemaCXX/attr-format-Float16.cpp
M clang/test/SemaCXX/attr-format.cpp
M clang/test/SemaCXX/format-strings-scanf.cpp
Log Message:
-----------
[Sema][test] Split format attribute test cases for _Float16
Fixes https://github.com/llvm/llvm-project/pull/74439#issuecomment-1880528376
Commit: 0ba868db709d2822b00f4ee9552d7fe41e5f2722
https://github.com/llvm/llvm-project/commit/0ba868db709d2822b00f4ee9552d7fe41e5f2722
Author: Javed Absar <106147771+javedabsar1 at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp
Log Message:
-----------
[MLIR][Bufferizer][NFC] Simplify some codes. (#77254)
NFC. clean up.
Commit: 27f547968cce89d4706ae2b27a0c15254d1670ee
https://github.com/llvm/llvm-project/commit/27f547968cce89d4706ae2b27a0c15254d1670ee
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Break after string literals with trailing line breaks (#76795)
This restores a subset of functionality that was forego in
d68826dfbd987377ef6771d40c1d984f09ee3b9e.
Streaming multiple string literals is rare enough in practice, hence
that change makes sense in general. But it seems people were
incidentally relying on this for having line breaks after string
literals that ended with `\n`.
This patch tries to restore that behavior to prevent regressions in the
upcoming LLVM release, until we can implement some configuration based
approach as proposed in https://github.com/llvm/llvm-project/pull/69859.
Commit: a831a21e4d8d41b044edaf61a90debb2ad756bda
https://github.com/llvm/llvm-project/commit/a831a21e4d8d41b044edaf61a90debb2ad756bda
Author: Mitch Phillips <31459023+hctim at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
M lld/test/ELF/aarch64-memtag-android-abi.s
Log Message:
-----------
[lld] [MTE] Allow android note for static executables. (#77078)
Florian pointed out that we're accidentally eliding the Android note for
static executables, as it's guarded behind the "can have memtag globals"
conditional. Of course, memtag globals are unsupported for static
executables, but we should still allow static binaries to produce the
Android note (as that's the only way they get MTE).
Commit: a9ffc92fc4428723e85485102dfe10fbea966e64
https://github.com/llvm/llvm-project/commit/a9ffc92fc4428723e85485102dfe10fbea966e64
Author: Nathan Gauër <brioche at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
A llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll
Log Message:
-----------
[SPIR-V] Add pre-headers to loops. (#75844)
This is the first of the 7 steps outlined in #75801. This PR explicitely
calls the SimplifyLoops pass. Directly following this pass should follow
the 6 others required to structurize the IR.
Running this pass could generate empty basic-blocks, which are implicit
fallthrough to the successor BB.
There was a specific condition in the SPIR-V ISel which handled implicit
fallthrough, but it couldn't work on empty basic-blocks. This commits
removes the old logic, and adds this new logic, which checks all
basic-blocks for implicit fallthroughs, including empty ones.
---------
Signed-off-by: Nathan Gauër <brioche at google.com>
Commit: 10b5b5d6e2df25dab86fe89a78c5df6f507f6e50
https://github.com/llvm/llvm-project/commit/10b5b5d6e2df25dab86fe89a78c5df6f507f6e50
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang] Fix a crash when referencing the result if the overload fails (#77288)
after 20a05677f9394d4bc9467fe7bc93a4ebd3aeda61
If the overload fails, the `Best` might point to the `end()`,
referencing it leads to asan crashes.
Commit: e35c912039a644a2cc44cf88f451f7a2cdc455d9
https://github.com/llvm/llvm-project/commit/e35c912039a644a2cc44cf88f451f7a2cdc455d9
Author: Liao Chunyu <chunyu at iscas.ac.cn>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV][NFC] Fix gcc -Wparentheses warning in RISCVISelDAGToDAG.cpp
warning:
RISCVISelDAGToDAG.cpp:767: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
767 | AM == ISD::POST_INC && "Unexpected addressing mode");
Commit: c8c525678e6dab2796c1996e0cdea31d4a865a9d
https://github.com/llvm/llvm-project/commit/c8c525678e6dab2796c1996e0cdea31d4a865a9d
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M flang/lib/Frontend/FrontendActions.cpp
Log Message:
-----------
[Flang] Remove unused triple variable. NFC (#77275)
I'm not sure why we don't get an unused variable warning, but triple
doesn't
seem to be used after 898db1136e679.
Commit: fb72a445c1abb21034dc4a63b8489f39150a5566
https://github.com/llvm/llvm-project/commit/fb72a445c1abb21034dc4a63b8489f39150a5566
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86CompressEVEX.cpp
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
Log Message:
-----------
[X86] Emit NDD2NonNDD entris in the EVEX comprerssion table, NFCI
This patch is a straightfoward change based on the design in #77202.
It does not have any effect since we haven't supported compressing ND
to non-ND in X86CompressEVEX.cpp.
Commit: 4fdd24b8d355e49d657c7c8a380b6f9b1b47ce1e
https://github.com/llvm/llvm-project/commit/4fdd24b8d355e49d657c7c8a380b6f9b1b47ce1e
Author: OCHyams <orlando.hyams at sony.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
Log Message:
-----------
[RemoveDIs][NFC] Update SelectionDAG test to check RemoveDIs mode too
In line with other RemoveDIs test updates. This test fails without #76941.
Commit: bdbaf6e61b63e24b94c85d7f71c11c212cd4cc9b
https://github.com/llvm/llvm-project/commit/bdbaf6e61b63e24b94c85d7f71c11c212cd4cc9b
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/bf16.ll
Log Message:
-----------
AMDGPU: Make v8bf16/v16bf16 legal types (#76678)
Depends #76217
Commit: 67782d2de5ea9c8653b8f0110237a3c355291c0e
https://github.com/llvm/llvm-project/commit/67782d2de5ea9c8653b8f0110237a3c355291c0e
Author: SiHuaN <liyongtai at iscas.ac.cn>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M flang/unittests/Runtime/ExternalIOTest.cpp
Log Message:
-----------
[flang] Remove duplicate tests. (#77059)
Commit: d218092543b3f9ba2204d7c8fe5ac70befa3d772
https://github.com/llvm/llvm-project/commit/d218092543b3f9ba2204d7c8fe5ac70befa3d772
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/test/Transforms/SCCP/switch.ll
Log Message:
-----------
[SCCP] Check whether the default case is reachable (#76295)
This patch eliminates unreachable default cases using range information.
Fixes #76085.
Commit: 8b49ed8ba1ba5ecd35bd1efa4be5a0f56b0135b8
https://github.com/llvm/llvm-project/commit/8b49ed8ba1ba5ecd35bd1efa4be5a0f56b0135b8
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py
Log Message:
-----------
[lldb][test] Skip DWARF inline source file test on Windows
This was added by 917b404e2ccdcc31d2d64971ad094b80967a240b
and fails for unknown reasons.
Commit: ba4cf31facdaf9bb9943c057d325ff0968331e9a
https://github.com/llvm/llvm-project/commit/ba4cf31facdaf9bb9943c057d325ff0968331e9a
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lldb/test/API/commands/expression/nested/TestNestedExpressions.py
Log Message:
-----------
[lldb][test] Skip part of nested expressions test on Windows
This was added by e42edb5547618c172abe25914000bb61f5278c4c and
has been failing: https://lab.llvm.org/buildbot/#/builders/219/builds/8012
Commit: eb523a4d272e81c8f7bf48da3923ed502f41c187
https://github.com/llvm/llvm-project/commit/eb523a4d272e81c8f7bf48da3923ed502f41c187
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/vec_extract-avx.ll
M llvm/test/CodeGen/X86/vec_extract-mmx.ll
M llvm/test/CodeGen/X86/vec_extract-sse4.ll
M llvm/test/CodeGen/X86/vec_extract.ll
Log Message:
-----------
[X86] vec_extract - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Commit: e3f8e44b00ecb95818bc68c693b6637460112b2a
https://github.com/llvm/llvm-project/commit/e3f8e44b00ecb95818bc68c693b6637460112b2a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-lzcnt-256.ll
M llvm/test/CodeGen/X86/vector-tzcnt-256.ll
Log Message:
-----------
[X86] vector-lzcnt-256.ll / vector-tzcnt-256.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Commit: f1e3a8f1eb7877b07d386af1a02cd7578a76c7d1
https://github.com/llvm/llvm-project/commit/f1e3a8f1eb7877b07d386af1a02cd7578a76c7d1
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/avx2-gather.ll
Log Message:
-----------
[X86] avx2-gather.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Commit: 0e4a38018a7228d93d72a31d9fae6855f866dded
https://github.com/llvm/llvm-project/commit/0e4a38018a7228d93d72a31d9fae6855f866dded
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/avx2-nontemporal.ll
Log Message:
-----------
[X86] avx2-nontemporal.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Commit: 2edce427a8b17d1d2192c1ee4a2227b6eb2971a0
https://github.com/llvm/llvm-project/commit/2edce427a8b17d1d2192c1ee4a2227b6eb2971a0
Author: Xing Xue <57193974+xingxue-ibm at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M openmp/CMakeLists.txt
M openmp/cmake/OpenMPTesting.cmake
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_global.cpp
M openmp/runtime/src/kmp_gsupport.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_wrapper_getpid.h
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/test/lit.cfg
Log Message:
-----------
[openmp][AIX]Initial changes for porting to AIX (#76841)
This PR contains initial changes for building and testing libomp on AIX.
More changes will follow.
- `KMP_OS_AIX` is defined for the AIX platform
- `KMP_ARCH_PPC` is defined for 32-bit PPC
- `KMP_ARCH_PPC_XCOFF` and `KMP_ARCH_PPC64_XCOFF` are for 32- and 64-bit
XCOFF object formats respectively
- Assembly file `z_AIX_asm.S` is used for AIX specific assembly code and
will be added in a separate PR
- The target library is disabled because AIX does not have the device
support
- OMPT is temporarily disabled
Commit: 763109e346b90193027b24743e266495d992b1c6
https://github.com/llvm/llvm-project/commit/763109e346b90193027b24743e266495d992b1c6
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
Log Message:
-----------
[mlir][gpu] Use `known_block_size` to set `maxntid` for NVVM target (#77301)
Setting thread block size with `maxntid` on the kernel has great
performance benefits. In this way, downstream PTX compiler can do better
register allocation.
MLIR's `gpu.launch` and `gpu.launch_func` already has an attribute
(`known_block_size`) that keeps the thread block size when it is known.
This PR simply uses this attribute to set `maxntid`.
Commit: 4a456489e051ff037655597a0b54654aa1f5a2a5
https://github.com/llvm/llvm-project/commit/4a456489e051ff037655597a0b54654aa1f5a2a5
Author: Kiran Chandramohan <kiran.chandramohan at arm.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90
M flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90
M flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90
M flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90
Log Message:
-----------
[Flang][OpenMP] Disable declarate target tests on Windows (#77306)
These tests seem to be failing in Windows bots.
See https://github.com/llvm/llvm-project/issues/77086
Commit: f0f16be77e1977d04535556ef69eaccd5bfef36f
https://github.com/llvm/llvm-project/commit/f0f16be77e1977d04535556ef69eaccd5bfef36f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
Log Message:
-----------
[clang][Sema][NFC] Clean up BuildOverloadedCallExpr
Commit: 7ca4473dd97328ebaa95dd3411e3c817935389de
https://github.com/llvm/llvm-project/commit/7ca4473dd97328ebaa95dd3411e3c817935389de
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
A llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
Log Message:
-----------
[AMDGPU] Add new cache flushing instructions for GFX12 (#76944)
Co-authored-by: Diana Picus <Diana-Magda.Picus at amd.com>
Commit: 2bf01d73f6ebca11f36c17a65b7a86109d44681e
https://github.com/llvm/llvm-project/commit/2bf01d73f6ebca11f36c17a65b7a86109d44681e
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
A lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp
A lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test
Log Message:
-----------
[lldb][DWARFASTParserClang] GetClangDeclForDIE: don't create VarDecl for static data members (#77155)
With DWARFv5, C++ static data members are represented as
`DW_TAG_variable`s (see `faa3a5ea9ae481da757dab1c95c589e2d5645982`).
In GetClangDeclForDIE, when trying to parse the `DW_AT_specification`
that a static data member's CU-level `DW_TAG_variable` points to, we
would try to `CreateVariableDeclaration`. Whereas previously it was a
no-op (for `DW_TAG_member`s). However, adding `VarDecls` to RecordDecls
for static data members should always be done in
`CreateStaticMemberVariable`. The test-case is an exapmle where we would
crash if we tried to create a `VarDecl` from within `GetClangDeclForDIE`
for a static data member.
This patch simply checks whether the `DW_TAG_variable` being parsed is a
static data member, and if so, trivially returns from
`GetClangDeclForDIE` (as we previously did for `DW_TAG_member`s).
Commit: b4ee7d6119f97931d9f38ac8c6bc7409eed87aab
https://github.com/llvm/llvm-project/commit/b4ee7d6119f97931d9f38ac8c6bc7409eed87aab
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
Log Message:
-----------
[lldb][DWARFIndex][nfc] Factor out fully qualified name query (#76977)
This moves the functionally of finding a DIE based on a fully qualified
name from SymbolFileDWARF into DWARFIndex itself, so that
specializations of DWARFIndex can implement faster versions of this
query.
Commit: ade7ae4760a0b0e74cddd8f852830ca946295930
https://github.com/llvm/llvm-project/commit/ade7ae4760a0b0e74cddd8f852830ca946295930
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/Transforms/InstSimplify/select.ll
Log Message:
-----------
[InstSimplify] Add test for #77320 (NFC)
Commit: 97e3220d6312ae00bcbe08673f218bd0f705776b
https://github.com/llvm/llvm-project/commit/97e3220d6312ae00bcbe08673f218bd0f705776b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstSimplify/select.ll
Log Message:
-----------
[InstSimplify] Consider bitcast as potential cross-lane operation
The bitcast might change the number of vector lanes, in which case
it will be a cross-lane operation.
Fixes https://github.com/llvm/llvm-project/issues/77320.
Commit: 16cd344380aa89a4bc47939ae65fd59fe8c77181
https://github.com/llvm/llvm-project/commit/16cd344380aa89a4bc47939ae65fd59fe8c77181
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
Log Message:
-----------
[RISCV] Fix collectNonISAExtFeature returning negative extension features (#76962)
collectNonISAExtFeature was returning any negative extension features,
e.g.
given an input of
+zifencei,+m,+a,+save-restore,-zbb,-relax,-zfa
It would return
+save-restore,-zbb,-relax,-zfa
Because negative extensions aren't emitted when calling
toFeatureVector(), and
so were considered missing. Hence why we still see "-zfa" and "-zfb" in
the tests for
the full arch string attributes, even though with a full arch string we
should be overriding the extensions.
This fixes it by using RISCVISAInfo::isSupportedExtensionFeature instead
to
check if a feature is an ISA extension.
Commit: e6b7c8c4951a470cc63a1721bc5f5ac7f3748a2f
https://github.com/llvm/llvm-project/commit/e6b7c8c4951a470cc63a1721bc5f5ac7f3748a2f
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
Log Message:
-----------
[OpenACC] Implement 'if' clause
The 'if' clause takes a required 'condition' expression. This patch
implements that as an expression we will later ensure is convertible to
a binary expression.
Commit: 0deb27c95722311c1ebedbbb8c8c4ac7735701fc
https://github.com/llvm/llvm-project/commit/0deb27c95722311c1ebedbbb8c8c4ac7735701fc
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90
M flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90
M flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap-enter.f90
M flang/test/Lower/OpenMP/declare-target-implicit-func-and-subr-cap.f90
Log Message:
-----------
Revert "[Flang][OpenMP] Disable declarate target tests on Windows" (#77324)
Reverts llvm/llvm-project#77306
These tests aren't broken on Windows, marking them XFAIL will just ~
consistently fail the build.
Commit: 036e48e2f5f890e1f9574cdb610e2336f12038a2
https://github.com/llvm/llvm-project/commit/036e48e2f5f890e1f9574cdb610e2336f12038a2
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll
Log Message:
-----------
[SLP]Fix PR76850: do the analysis of the submask.
Need to limit the transformation of the VecMask by the corresponding part of the mask of SliceSize size to avoid compiler crash during further cost analysis.
Commit: 34dbaddc6fa1ce0892ecf3ca06866e7038b2a9b3
https://github.com/llvm/llvm-project/commit/34dbaddc6fa1ce0892ecf3ca06866e7038b2a9b3
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
Log Message:
-----------
[clang][ASTImporter] Only reorder fields of RecordDecls (#77079)
Prior to `e9536698720ec524cc8b72599363622bc1a31558`
(https://reviews.llvm.org/D154764) we only re-ordered the fields of
`RecordDecl`s. The change refactored this logic to make sure
`FieldDecl`s are imported before other member decls. However, this
change also widened the types of `DeclContext`s we consider for
re-ordering from `RecordDecl` to anything that's a `DeclContext`. This
seems to have been just a drive-by cleanup.
Internally we've seen numerous crashes in LLDB where we try to perform
this re-ordering on fields of `ObjCInterfaceDecl`s.
This patch restores old behaviour where we limit the re-ordering to just
`RecordDecl`s.
rdar://119343184
rdar://119636274
rdar://119832131
Commit: 69066ab31959968ebcbca71f3872bdedef8fb8cd
https://github.com/llvm/llvm-project/commit/69066ab31959968ebcbca71f3872bdedef8fb8cd
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
M clang/test/CXX/over/over.load/p2-0x.cpp
Log Message:
-----------
[Clang] Fix IsOverload for function templates (#77323)
Functions which correspond but have different template parameter lists
are not redeclarations.
Fixes a regression introduced by af4751
(The patch just moves the template parameters check above if the
signature check)
Fixes #76358
Commit: bda562519b89ea3832be00d8ac75cfcdb924dce2
https://github.com/llvm/llvm-project/commit/bda562519b89ea3832be00d8ac75cfcdb924dce2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
Log Message:
-----------
[Libomptarget][NFC] Fix unhandled allocator enum value
Commit: 01410103a6eb50436c39f71299773749b7de9dec
https://github.com/llvm/llvm-project/commit/01410103a6eb50436c39f71299773749b7de9dec
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libcxx/docs/Status/Cxx20Issues.csv
Log Message:
-----------
[libc++][doc] Marks LWG3257 as complete (#77237)
The macros were already updated
- __cpp_lib_string_view in 466df1718e41fe2fca6ce6bd98c01b18f42c05e4
- __cpp_lib_array_constexpr in 77b9abfc8e89ca627e4f9a1cc206bea131db6db1
Based on the dates of the commit and that
P0858 "Constexpr iterator requirements"
was completed in LLVM 12, set this issue as completed in the same
version.
Completes
- LWG3257 Missing feature testing macro update from P0858
Commit: 053aed2024a1014736ffe35b001710b263c7a4b5
https://github.com/llvm/llvm-project/commit/053aed2024a1014736ffe35b001710b263c7a4b5
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Check if machine loop is passed while getting loop alignment (#77283)
After d6bb96e677759375b2bea00115918b2cb6552f5b, calling
getPrefLoopAlignment without passing in a pointer to a MachineLoop
causes a segmentation fault. This conflicts with the API in
TargetLoweringBase where the default MachineLoop pointer passed is
nullptr. This patch fixes this by checking if the pointer points to
something before enabling the optional functionality.
Commit: ff47989ec238dafe4a68c6a716e8dbccc9f559f5
https://github.com/llvm/llvm-project/commit/ff47989ec238dafe4a68c6a716e8dbccc9f559f5
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
Log Message:
-----------
[AArch64][GlobalISel] Allow anyexting loads from 32b -> 64b to be legal.
We can already support selection of these through imported patterns, we were
just missing the legalizer rule to allow these to be formed.
Nano size benefit overall.
Commit: 12101ca8e322c4cbf40e44b5b1fbf7ea76aff581
https://github.com/llvm/llvm-project/commit/12101ca8e322c4cbf40e44b5b1fbf7ea76aff581
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libc/src/__support/threads/linux/CMakeLists.txt
Log Message:
-----------
[libc] set -Wno-frame-address for thread.cpp (#77140)
The aarch64 code is using __builtin_return_address with a non-zero
parameter,
which generates the following warning:
llvm-project/libc/src/__support/threads/linux/thread.cpp:171:38: error:
calling '__builtin_frame_address' with a nonzero argument is unsafe
[-Werror,-Wframe-address]
171 | return reinterpret_cast<uintptr_t>(__builtin_frame_address(1));
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
Disable this diagnostic just for this file so that we can enable
-Werror.
Fixes: #77007
Commit: 0e7199cf3d08c83d18549c9cd083e9fec6e9db54
https://github.com/llvm/llvm-project/commit/0e7199cf3d08c83d18549c9cd083e9fec6e9db54
Author: arpilipe <apilipenko at azul.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/test/Other/print-at-pass-number.ll
Log Message:
-----------
Replace print-at-pass-number cl::opt with print-before-pass-number (#76211)
The existing option prints the IR after the pass, but it's not clear
from its name. In this patch I change the option to print the IR before
the pass and change the name to make the behavior clear.
Printing the IR before the pass is slightly simpler than after as I
don't need to worry about printAfterPassInvalidated case. Either before
or after the pass would be ok for the original use case this option was
introduced for.
Commit: c68a9d25e99a096f6862fc4b57dd380a21245d31
https://github.com/llvm/llvm-project/commit/c68a9d25e99a096f6862fc4b57dd380a21245d31
Author: Tacet <advenam.tacet at trailofbits.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[ASan][libc++] String annotations optimizations fix with lambda (#76200)
This commit addresses optimization and instrumentation challenges
encountered within comma constructors.
1) _LIBCPP_STRING_INTERNAL_MEMORY_ACCESS does not work in comma
constructors.
2) Code inside comma constructors is not always correctly optimized.
Problematic code examples:
- `: __r_(((__str.__is_long() ? 0 : (__str.__annotate_delete(), 0)),
std::move(__str.__r_))) {`
- `: __r_(__r_([&](){ if(!__s.__is_long()) __s.__annotate_delete();
return std::move(__s.__r_);}())) {`
However, lambda with argument seems to be correctly optimized. The patch employs this.
Use of lambda based on an idea from @ldionne.
Commit: c52b467875e26d5d3554514489d965eda3ab0cd2
https://github.com/llvm/llvm-project/commit/c52b467875e26d5d3554514489d965eda3ab0cd2
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/docs/dev/code_style.rst
Log Message:
-----------
Reapply "[libc] build with -Werror (#73966)" (#74506)
This reverts commit 6886a52d6dbefff77f33de12ff85d654e2557f81.
Most of the errors observed in postsubmit have been addressed. We can
fix-forward the remaining ones.
Link: https://lab.llvm.org/buildbot/#/changes/117129
Commit: f3f66773117259185b76574de9385e25e3902658
https://github.com/llvm/llvm-project/commit/f3f66773117259185b76574de9385e25e3902658
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/combine-bextr.ll
Log Message:
-----------
[X86] combine-bextr.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Add nounwind to remove cfi noise as well.
Commit: 61dcfaa745e22b0e5330fc82ee4b7de4b6c99ab7
https://github.com/llvm/llvm-project/commit/61dcfaa745e22b0e5330fc82ee4b7de4b6c99ab7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/i64-mem-copy.ll
Log Message:
-----------
[X86] i64-mem-copy.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Add nounwind to remove cfi noise as well.
Commit: 8bd16789ff0af00270936c4536dd18b48e4d3897
https://github.com/llvm/llvm-project/commit/8bd16789ff0af00270936c4536dd18b48e4d3897
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/lea-2.ll
Log Message:
-----------
[X86] lea-2.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only (although in this case the gnux32 tests share the X64 checks)
Commit: 635f6d384596950e73b2485842c587a2954c655f
https://github.com/llvm/llvm-project/commit/635f6d384596950e73b2485842c587a2954c655f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/inline-sse.ll
Log Message:
-----------
[X86] inline-sse.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Commit: 9632f987161b4efeb8c087f19a3eb4f7c69cc920
https://github.com/llvm/llvm-project/commit/9632f987161b4efeb8c087f19a3eb4f7c69cc920
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/legalize-shl-vec.ll
Log Message:
-----------
[X86] legalize-shl-vec.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Add nounwind to remove cfi noise as well.
Commit: fbfc9cb7ea756ea645cc55eea478b819573fc7a5
https://github.com/llvm/llvm-project/commit/fbfc9cb7ea756ea645cc55eea478b819573fc7a5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
Log Message:
-----------
[X86] vector-shuffle-mmx.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Add nounwind to remove cfi noise as well.
Commit: 52ebf61bac9d17a960908fe0c5e75dea76de165a
https://github.com/llvm/llvm-project/commit/52ebf61bac9d17a960908fe0c5e75dea76de165a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/ftrunc.ll
Log Message:
-----------
[X86] ftrunc.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
Add common AVX check prefix for 32/64 bit test coverage
Commit: a14650572c2752c0e08a66ce94c43578abf378f8
https://github.com/llvm/llvm-project/commit/a14650572c2752c0e08a66ce94c43578abf378f8
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaInit.cpp
Log Message:
-----------
[Sema] Clean up -Wc++11-narrowing-const-reference code after #76094. NFC (#77278)
Commit: 61968286f9a39815040b0d94299c3732834661bf
https://github.com/llvm/llvm-project/commit/61968286f9a39815040b0d94299c3732834661bf
Author: Karthika Devi C <quic_kartc at quicinc.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M polly/lib/Transform/ScheduleOptimizer.cpp
A polly/test/ScheduleOptimizer/schedule_computeout.ll
Log Message:
-----------
[polly][ScheduleOptimizer] Reland Fix long compile time(hang) reported in polly (#77280)
There is no upper cap set on current Schedule Optimizer to compute
schedule. In some cases a very long compile time taken to compute the
schedule resulting in hang kind of behavior. This patch introduces a
flag 'polly-schedule-computeout' to pass the capwhich is initialized to
300000. This patch handles the compute out cases by bailing out and
exiting gracefully.
Fixed the test that failed in previous commit.
Fixes #69090
Commit: de15c5501903a5a52dcae976e40b8b1f6a838911
https://github.com/llvm/llvm-project/commit/de15c5501903a5a52dcae976e40b8b1f6a838911
Author: Craig Hesling <craig at hesling.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
Revert "[GitHub] Fix slow sccache install on macOS by upgrading macOS version (#77165)" (#77270)
This reverts commit 602c8fa2d8da6562e4f36df3bd63c26a4c7461e7, due to an
sccache issue seen on larger builds using macOS-12 runners.
The issue is documented in in the following issue:
https://github.com/hendrikmuhs/ccache-action/issues/174
The original PR is the following:
https://github.com/llvm/llvm-project/pull/77165
Commit: 5351ded68d579921a61b26a34e36046c22f668bd
https://github.com/llvm/llvm-project/commit/5351ded68d579921a61b26a34e36046c22f668bd
Author: Tacet <advenam.tacet at trailofbits.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libcxx/include/sstream
Log Message:
-----------
[libc++] Remove usage of internal string function in sstream (#75858)
This function replaces a call to `__move_assign` (internal function)
with two calls to public member functions (`resize` and `erase`). The
order of calls is chosen for the best performance.
This change is required to [turn on ASan string annotations for short
strings](https://github.com/llvm/llvm-project/pull/75882) (Short String
Optimization - SSO).
The `std::basic_string` class's `void __move_assign(basic_string&&
__str, size_type __pos, size_type __len)` function operates on
uninitialized strings, where it is reasonable to assume that the memory
is not poisoned. However, in `sstream` this function is applied to
existing strings that already have poisoned memory.
String ASan annotations turned on here:
https://github.com/llvm/llvm-project/pull/72677
Commit: d460c1de3b989cea919b9d60c21644f28f987950
https://github.com/llvm/llvm-project/commit/d460c1de3b989cea919b9d60c21644f28f987950
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/vselect-ext.ll
M llvm/test/CodeGen/SystemZ/vec-perm-14.ll
M llvm/test/CodeGen/X86/test-shrink-bug.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
Log Message:
-----------
[DAG] SimplifyDemandedBits - don't fold sext(x) -> aext(x) if we lose an 0/-1 allsignbits mask (#77296)
For targets that use 0/-1 boolean results, we want to keep this pattern through extensions/truncations as much as possible - so avoid simplifying to any_extend even if we don't demand the upper bits.
Noticed in triage for https://reviews.llvm.org/D152928
Commit: 4c66180e46eaed0cd6aa37102a1e3b37cc9d85fa
https://github.com/llvm/llvm-project/commit/4c66180e46eaed0cd6aa37102a1e3b37cc9d85fa
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV] Use COPY to create artificial 64-bit uses in RISCVOptWInstrs's tests
In reflection of 4dd5d967975fa8d52b8c60596d892d9dd5615809, we can now
use COPY to physical registers to create artificial 64-bit uses to
prevent RISCVOptWInstrs from optimizing away sext in absent of the
IsSignExtendingOpW flag.
NFCI.
Commit: c1023c585de2629911a529cdf32490b99df83345
https://github.com/llvm/llvm-project/commit/c1023c585de2629911a529cdf32490b99df83345
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M libc/src/__support/HashTable/generic/bitmask_impl.inc
M libc/src/__support/HashTable/table.h
Log Message:
-----------
[libc] fix -Wmissing-braces (#77345)
Fixes the following errors observed on the aarch64 fullbuild:
/home/libc-buildbot/libc-aarch64-ubuntu/libc-aarch64-ubuntu-fullbuild-dbg/llvm-project/libc/src/__support/HashTable/generic/bitmask_impl.inc:116:13:
error: suggest braces around initialization of subobject
[-Werror,-Wmissing-braces]
return {static_cast<bitmask_t>(mask_available().word ^
repeat_byte(0x80))};
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
{ }
In file included from
/home/libc-buildbot/libc-aarch64-ubuntu/libc-aarch64-ubuntu-fullbuild-dbg/llvm-project/libc/src/search/hdestroy.cpp:10:
/home/libc-buildbot/libc-aarch64-ubuntu/libc-aarch64-ubuntu-fullbuild-dbg/llvm-project/libc/src/__support/HashTable/table.h:336:41:
error: suggest braces around initialization of subobject
[-Werror,-Wmissing-braces]
iterator end() const { return {0, 0, {0}, *this}; }
^
{}
Link:
https://lab.llvm.org/buildbot/#/builders/223/builds/33868/steps/6/logs/stdio
Link: https://github.com/llvm/llvm-project/pull/74506
Commit: eb42868f25665ba6301a94a30e9df33e0d6ae61f
https://github.com/llvm/llvm-project/commit/eb42868f25665ba6301a94a30e9df33e0d6ae61f
Author: Billy Zhu <billyzhu at modular.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/test/Transforms/canonicalize.mlir
Log Message:
-----------
[MLIR] Handle materializeConstant failure in GreedyPatternRewriteDriver (#77258)
Make GreedyPatternRewriteDriver handle failures of `materializeConstant`
gracefully. Previously it was not checking whether the returned op was
null and crashing. This PR handles it similarly to how OperationFolder
does it.
Commit: 07d6fbf8d80083470b4371f2ddabd656a9c317e6
https://github.com/llvm/llvm-project/commit/07d6fbf8d80083470b4371f2ddabd656a9c317e6
Author: Alex Langford <alangford at apple.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/BreakpointIDList.h
M lldb/source/Breakpoint/BreakpointIDList.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
Log Message:
-----------
[lldb][NFCI] Remove BreakpointIDList::InsertStringArray (#77161)
This abstraction is leaky and BreakpointIDList does not need to know
about CommandReturnObject.
Additionally, setting the CommandReturnObject inout param to a success
state does very little. The function returns immediately if the input
ArrayRef is empty, and reading
CommandObjectMultiwordBreakpoint::VerifyIDs more closely, the input is
always empty if the previous call to
BreakpointIDList::FindAndReplaceIDRanges failed. If the call was
successful, then the CommandReturnObject is already in a success state.
I have opted to remove the function altogether and inline the
functionality where it was used.
Commit: 5cbf74b012c10e9cc841a27cd5d7335e556f47dd
https://github.com/llvm/llvm-project/commit/5cbf74b012c10e9cc841a27cd5d7335e556f47dd
Author: Alex Langford <alangford at apple.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/BreakpointIDList.h
M lldb/source/Breakpoint/BreakpointIDList.cpp
Log Message:
-----------
[lldb][NFCI] Change return type of BreakpointIDList::GetBreakpointIDAtIndex (#77166)
There are 2 motivations here:
1.) There is no need to hand out constant references to BreakpointIDs,
they are only 8 bytes big. In addition, every use of this method already
makes a copy anyway.
2.) Each BreakpointIDList held onto an invalid BreakpointID specifically
to
prevent lifetime issues. Returning a value means you can return an
invalid BreakpointID instead of needing to allocate storage for an
invalid BreakpointID.
Commit: 478ec63312582c24c8d6ecab280da2380137c0b7
https://github.com/llvm/llvm-project/commit/478ec63312582c24c8d6ecab280da2380137c0b7
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV] Mark VFIRST and VCPOP as SignExtendingOpW (#77022)
Since their values are small enough ([-1, 65535] & [0, 65535],
respectively) to fit into signed 32 bits, any sext (or downcasting +
sext) will be redundnat. Hence marking them as SignExtendingOpW.
Commit: f4bc70e886f2eb1b646d84871b93897db749c826
https://github.com/llvm/llvm-project/commit/f4bc70e886f2eb1b646d84871b93897db749c826
Author: Juergen Ributzka <juergen at ributzka.de>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M clang/lib/Lex/ModuleMap.cpp
R clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd
R clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h
R clang/test/Modules/autolinkTBD.m
A clang/test/Modules/autolink_private_module.m
Log Message:
-----------
[clang][modules] Remove `_Private` suffix from framework auto-link hints. (#77120)
- [clang][modules] Remove no longer needed autolink test for TBD files.
- [clang][modules] Remove `_Private` suffix from framework auto-link
hints.
Commit: 23e03a85dc665c784c8b77d429f0f0e2e6d0c2fe
https://github.com/llvm/llvm-project/commit/23e03a85dc665c784c8b77d429f0f0e2e6d0c2fe
Author: Min-Yih Hsu <min.hsu at sifive.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M bolt/test/RISCV/relax.s
Log Message:
-----------
[BOLT] Update test case after #77253
PR #77253 removed the '@plt' suffix from callee symbols. Update
RISCV/relax.s accordingly.
Commit: daa4728deed3d222ff163cfb963321938549ddf1
https://github.com/llvm/llvm-project/commit/daa4728deed3d222ff163cfb963321938549ddf1
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
Log Message:
-----------
[AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (#75825)
Commit: e7655ad605d77e206ec94b2cef59c41a508edba7
https://github.com/llvm/llvm-project/commit/e7655ad605d77e206ec94b2cef59c41a508edba7
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
[Libomptarget] Remove unnecessary CMake definition of endiannness (#77205)
Summary:
This is needed for some definition in `hsa.h` that requires this to be
set for some architectures when it fails at autodetection. We only
really build `libomptarget` with `gcc` and `clang` which already provide
their own way of detecting this. Remove the unnecessary define and move
it into the source.
Commit: b2845d6945cf560e26f98128d06b22e85953612d
https://github.com/llvm/llvm-project/commit/b2845d6945cf560e26f98128d06b22e85953612d
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
A .github/workflows/libclang-python-tests.yml
M .github/workflows/llvm-project-tests.yml
M bolt/test/RISCV/relax.s
M clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/AST/Interp/arrays.cpp
M clang/test/CXX/over/over.load/p2-0x.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
M clang/test/Driver/linker-wrapper-image.c
M clang/test/Driver/mingw-sysroot.cpp
M clang/test/Driver/riscv-rvv-vector-bits.c
R clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd
R clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h
R clang/test/Modules/autolinkTBD.m
A clang/test/Modules/autolink_private_module.m
A clang/test/Modules/explicit-specializations.cppm
M clang/test/ParserOpenACC/parse-clauses.c
A clang/test/Sema/attr-format-Float16.c
A clang/test/SemaCXX/attr-format-Float16.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/lib/msan/msan.h
M compiler-rt/lib/msan/msan_allocator.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp
M flang/test/Transforms/debug-line-table-existing.fir
M flang/test/Transforms/debug-line-table-inc-file.fir
M flang/test/Transforms/debug-line-table.fir
M flang/unittests/Runtime/ExternalIOTest.cpp
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/docs/dev/code_style.rst
M libc/include/CMakeLists.txt
M libc/src/__support/HashTable/generic/bitmask_impl.inc
M libc/src/__support/HashTable/table.h
M libc/src/__support/StringUtil/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
M libcxx/cmake/caches/Armv7M-picolibc.cmake
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/18.rst
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/fstream
M libcxx/include/sstream
M libcxx/include/string
M libcxx/include/tuple
M libcxx/include/version
M libcxx/src/CMakeLists.txt
A libcxx/src/fstream.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp
A libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/fstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/fstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/native_handle_assert_test_helpers.h
A libcxx/test/std/input.output/file.streams/fstreams/native_handle_test_helpers.h
A libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream/types.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/types.h
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/qemu_baremetal.py
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
M lld/test/ELF/aarch64-memtag-android-abi.s
A lld/test/ELF/eh-frame-nonzero-offset-riscv.s
R lld/test/ELF/linkerscript/overlay-reject.test
R lld/test/ELF/linkerscript/overlay-reject2.test
M lld/test/ELF/linkerscript/overlay.test
M lld/test/ELF/x86-64-tls-pie.s
M lldb/include/lldb/Breakpoint/BreakpointIDList.h
M lldb/source/Breakpoint/BreakpointIDList.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/test/API/commands/expression/nested/TestNestedExpressions.py
M lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py
A lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp
A lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/MemoryBuiltins.h
M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
M llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/lib/Analysis/VFABIDemangling.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SwitchLoweringUtils.cpp
M llvm/lib/DWARFLinker/DWARFStreamer.cpp
M llvm/lib/DWARFLinkerParallel/DebugLineSectionEmitter.h
M llvm/lib/DWARFLinkerParallel/OutputSections.cpp
M llvm/lib/DWARFLinkerParallel/OutputSections.h
M llvm/lib/Object/ELF.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/ARM/ARMLegalizerInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
M llvm/lib/Target/X86/X86.h
A llvm/lib/Target/X86/X86CompressEVEX.cpp
R llvm/lib/Target/X86/X86EvexToVex.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFormats.td
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vselect-ext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
A llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
A llvm/test/CodeGen/LoongArch/global-variable-code-model.ll
A llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/addrspacecast.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/analyze-branch.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-frem.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/byval.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-fcmp.ll
M llvm/test/CodeGen/RISCV/double-frem.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/emutls.ll
M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fli-licm.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-fcmp.ll
M llvm/test/CodeGen/RISCV/float-frem.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-mem.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fp16-promote.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/frame-info.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-frem.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/make-compressible.mir
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/mir-target-flags.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/nest-register.ll
M llvm/test/CodeGen/RISCV/nomerge.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rem.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64-large-stack.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/split-sp-adjust.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-protector-target.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tls-models.ll
M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/vector-abi.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
A llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll
M llvm/test/CodeGen/SystemZ/vec-perm-14.ll
M llvm/test/CodeGen/X86/O0-pipeline.ll
M llvm/test/CodeGen/X86/avx2-gather.ll
M llvm/test/CodeGen/X86/avx2-nontemporal.ll
M llvm/test/CodeGen/X86/combine-bextr.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
M llvm/test/CodeGen/X86/ftrunc.ll
M llvm/test/CodeGen/X86/i64-mem-copy.ll
M llvm/test/CodeGen/X86/inline-sse.ll
M llvm/test/CodeGen/X86/invpcid-intrinsic.ll
M llvm/test/CodeGen/X86/lea-2.ll
M llvm/test/CodeGen/X86/legalize-shl-vec.ll
M llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll
M llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/sha.ll
M llvm/test/CodeGen/X86/test-shrink-bug.ll
M llvm/test/CodeGen/X86/vec_extract-avx.ll
M llvm/test/CodeGen/X86/vec_extract-mmx.ll
M llvm/test/CodeGen/X86/vec_extract-sse4.ll
M llvm/test/CodeGen/X86/vec_extract.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vector-lzcnt-256.ll
M llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
M llvm/test/CodeGen/X86/vector-tzcnt-256.ll
M llvm/test/CodeGen/X86/x64-cet-intrinsics.ll
M llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll
M llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll
M llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll
M llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
M llvm/test/Instrumentation/InstrProfiling/platform.ll
M llvm/test/Instrumentation/InstrProfiling/profiling.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
M llvm/test/MC/RISCV/function-call.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/Other/print-at-pass-number.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll
M llvm/test/Transforms/InstCombine/icmp.ll
M llvm/test/Transforms/InstSimplify/select.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
M llvm/test/Transforms/SCCP/switch.ll
A llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll
A llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll
M llvm/test/tools/dsymutil/ARM/dwarf5-dwarf4-combination-macho.test
M llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
M llvm/test/tools/llvm-dwarfdump/AArch64/verify-no-file.yaml
M llvm/unittests/Analysis/VectorFunctionABITest.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/utils/TableGen/CMakeLists.txt
A llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
R llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
M llvm/utils/TableGen/X86FoldTablesEmitter.cpp
A llvm/utils/TableGen/X86ManualCompressEVEXTables.def
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
M mlir/examples/toy/Ch6/toyc.cpp
M mlir/examples/toy/Ch7/toyc.cpp
A mlir/include/mlir/Analysis/Presburger/Barvinok.h
A mlir/include/mlir/Analysis/Presburger/GeneratingFunction.h
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/BufferUtils.h
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
M mlir/include/mlir/ExecutionEngine/RunnerUtils.h
M mlir/include/mlir/IR/Dominance.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
A mlir/lib/Analysis/Presburger/Barvinok.cpp
M mlir/lib/Analysis/Presburger/CMakeLists.txt
R mlir/lib/Analysis/Presburger/GeneratingFunction.h
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.h
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/python/mlir/ir.py
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
M mlir/test/Conversion/MemRefToSPIRV/bitwidth-emulation.mlir
M mlir/test/Conversion/SCFToGPU/no_blocks_no_threads.mlir
M mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/outlining.mlir
M mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir
M mlir/test/Dialect/LLVMIR/call-location.mlir
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
M mlir/test/Dialect/LLVMIR/global.mlir
M mlir/test/Dialect/LLVMIR/inlining.mlir
M mlir/test/Dialect/LLVMIR/invalid-call-location.mlir
M mlir/test/Dialect/LLVMIR/loop-metadata.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
M mlir/test/Dialect/SPIRV/IR/availability.mlir
M mlir/test/Dialect/SPIRV/IR/cast-ops.mlir
M mlir/test/Dialect/SPIRV/IR/function-decorations.mlir
M mlir/test/Dialect/SPIRV/IR/target-env.mlir
M mlir/test/Dialect/SPIRV/Transforms/inlining.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/loop-metadata.mlir
M mlir/test/Target/SPIRV/atomic-ops.mlir
M mlir/test/Target/SPIRV/cast-ops.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/function-decorations.mlir
M mlir/test/Transforms/canonicalize.mlir
M mlir/test/python/dialects/memref.py
A mlir/unittests/Analysis/Presburger/BarvinokTest.cpp
M mlir/unittests/Analysis/Presburger/CMakeLists.txt
A mlir/unittests/Analysis/Presburger/GeneratingFunctionTest.cpp
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
M mlir/unittests/Analysis/Presburger/Utils.h
M openmp/CMakeLists.txt
M openmp/cmake/OpenMPTesting.cmake
M openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
M openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_global.cpp
M openmp/runtime/src/kmp_gsupport.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_wrapper_getpid.h
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/test/lit.cfg
M polly/lib/Transform/ScheduleOptimizer.cpp
A polly/test/ScheduleOptimizer/schedule_computeout.ll
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 4301f9aa15dda7f605ab85f925f3f8cf40c3bca6
https://github.com/llvm/llvm-project/commit/4301f9aa15dda7f605ab85f925f3f8cf40c3bca6
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-01-08 (Mon, 08 Jan 2024)
Changed paths:
A .github/workflows/libclang-python-tests.yml
M .github/workflows/llvm-project-tests.yml
M bolt/test/RISCV/relax.s
M clang-tools-extra/clang-tidy/cppcoreguidelines/MissingStdForwardCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/missing-std-forward.cpp
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/FormatString.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Driver/ToolChains/MinGW.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Lex/ModuleMap.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/AST/Interp/arrays.cpp
M clang/test/CXX/over/over.load/p2-0x.cpp
M clang/test/CXX/temp/temp.arg/temp.arg.template/p3-2a.cpp
M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
M clang/test/Driver/linker-wrapper-image.c
M clang/test/Driver/mingw-sysroot.cpp
M clang/test/Driver/riscv-rvv-vector-bits.c
R clang/test/Modules/Inputs/AutolinkTBD.framework/AutolinkTBD.tbd
R clang/test/Modules/Inputs/AutolinkTBD.framework/Headers/AutolinkTBD.h
R clang/test/Modules/autolinkTBD.m
A clang/test/Modules/autolink_private_module.m
A clang/test/Modules/explicit-specializations.cppm
M clang/test/ParserOpenACC/parse-clauses.c
A clang/test/Sema/attr-format-Float16.c
A clang/test/SemaCXX/attr-format-Float16.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M compiler-rt/lib/msan/msan.h
M compiler-rt/lib/msan/msan_allocator.cpp
M compiler-rt/lib/msan/msan_new_delete.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Transforms/AddDebugFoundation.cpp
M flang/test/Transforms/debug-line-table-existing.fir
M flang/test/Transforms/debug-line-table-inc-file.fir
M flang/test/Transforms/debug-line-table.fir
M flang/unittests/Runtime/ExternalIOTest.cpp
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/docs/dev/code_style.rst
M libc/include/CMakeLists.txt
M libc/src/__support/HashTable/generic/bitmask_impl.inc
M libc/src/__support/HashTable/table.h
M libc/src/__support/StringUtil/CMakeLists.txt
M libc/src/__support/threads/linux/CMakeLists.txt
M libcxx/cmake/caches/Armv7M-picolibc.cmake
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/18.rst
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/docs/Status/Cxx2cPapers.csv
M libcxx/include/fstream
M libcxx/include/sstream
M libcxx/include/string
M libcxx/include/tuple
M libcxx/include/version
M libcxx/src/CMakeLists.txt
A libcxx/src/fstream.cpp
M libcxx/test/libcxx/utilities/expected/expected.expected/transform_error.mandates.verify.cpp
M libcxx/test/libcxx/utilities/expected/expected.void/transform_error.mandates.verify.cpp
A libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/filebuf.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/filebuf/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/fstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/fstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/fstream/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ifstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ifstream/types.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/native_handle_assert_test_helpers.h
A libcxx/test/std/input.output/file.streams/fstreams/native_handle_test_helpers.h
A libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/native_handle.assert.pass.cpp
A libcxx/test/std/input.output/file.streams/fstreams/ofstream.members/native_handle.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/ofstream/types.pass.cpp
M libcxx/test/std/input.output/file.streams/fstreams/types.h
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
M libcxx/utils/qemu_baremetal.py
M lld/ELF/Arch/AArch64.cpp
M lld/ELF/Arch/X86_64.cpp
M lld/ELF/SyntheticSections.cpp
M lld/ELF/Writer.cpp
M lld/ELF/Writer.h
M lld/test/ELF/aarch64-memtag-android-abi.s
A lld/test/ELF/eh-frame-nonzero-offset-riscv.s
R lld/test/ELF/linkerscript/overlay-reject.test
R lld/test/ELF/linkerscript/overlay-reject2.test
M lld/test/ELF/linkerscript/overlay.test
M lld/test/ELF/x86-64-tls-pie.s
M lldb/include/lldb/Breakpoint/BreakpointIDList.h
M lldb/source/Breakpoint/BreakpointIDList.cpp
M lldb/source/Commands/CommandObjectBreakpoint.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFASTParserClang.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFIndex.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/test/API/commands/expression/nested/TestNestedExpressions.py
M lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py
A lldb/test/Shell/SymbolFile/DWARF/Inputs/dwo-static-data-member.cpp
A lldb/test/Shell/SymbolFile/DWARF/dwo-static-data-member-access.test
M llvm/docs/LangRef.rst
M llvm/include/llvm/Analysis/MemoryBuiltins.h
M llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
M llvm/include/llvm/CodeGen/SwitchLoweringUtils.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/Passes/StandardInstrumentations.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/lib/Analysis/VFABIDemangling.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/SwitchLoweringUtils.cpp
M llvm/lib/DWARFLinker/DWARFStreamer.cpp
M llvm/lib/DWARFLinkerParallel/DebugLineSectionEmitter.h
M llvm/lib/DWARFLinkerParallel/OutputSections.cpp
M llvm/lib/DWARFLinkerParallel/OutputSections.h
M llvm/lib/Object/ELF.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUCombine.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/ARM/ARMLegalizerInfo.h
M llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchISelLowering.h
M llvm/lib/Target/M68k/GISel/M68kLegalizerInfo.h
M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.cpp
M llvm/lib/Target/SPIRV/SPIRVUtils.h
M llvm/lib/Target/X86/CMakeLists.txt
M llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
M llvm/lib/Target/X86/X86.h
A llvm/lib/Target/X86/X86CompressEVEX.cpp
R llvm/lib/Target/X86/X86EvexToVex.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrFormats.td
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86TargetMachine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Utils/SCCPSolver.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
A llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-split.ll
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/arm64-zip.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll
R llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-armpl.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-sleef-scalable.ll
A llvm/test/CodeGen/AArch64/replace-with-veclib-sleef.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AArch64/vselect-ext.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
A llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
A llvm/test/CodeGen/LoongArch/global-variable-code-model.ll
A llvm/test/CodeGen/PowerPC/intrinsic-trap.ll
M llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64d.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calls.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vararg.ll
M llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/variadic-call.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-bswap-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-div-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-fp-ceil-floor.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mul-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-mulo-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rem-rv64.mir
M llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
M llvm/test/CodeGen/RISCV/addrspacecast.ll
M llvm/test/CodeGen/RISCV/aext-to-sext.ll
M llvm/test/CodeGen/RISCV/alloca.ll
M llvm/test/CodeGen/RISCV/analyze-branch.ll
M llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
M llvm/test/CodeGen/RISCV/atomic-load-store.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
M llvm/test/CodeGen/RISCV/atomic-rmw-sub.ll
M llvm/test/CodeGen/RISCV/atomic-rmw.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
M llvm/test/CodeGen/RISCV/bf16-promote.ll
M llvm/test/CodeGen/RISCV/bfloat-br-fcmp.ll
M llvm/test/CodeGen/RISCV/bfloat-convert.ll
M llvm/test/CodeGen/RISCV/bfloat-frem.ll
M llvm/test/CodeGen/RISCV/bfloat-mem.ll
M llvm/test/CodeGen/RISCV/bfloat.ll
M llvm/test/CodeGen/RISCV/bittest.ll
M llvm/test/CodeGen/RISCV/byval.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
M llvm/test/CodeGen/RISCV/calling-conv-half.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
M llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
M llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
M llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
M llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/copysign-casts.ll
M llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/div-by-constant.ll
M llvm/test/CodeGen/RISCV/div.ll
M llvm/test/CodeGen/RISCV/double-arith-strict.ll
M llvm/test/CodeGen/RISCV/double-arith.ll
M llvm/test/CodeGen/RISCV/double-br-fcmp.ll
M llvm/test/CodeGen/RISCV/double-calling-conv.ll
M llvm/test/CodeGen/RISCV/double-convert-strict.ll
M llvm/test/CodeGen/RISCV/double-convert.ll
M llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/double-fcmp.ll
M llvm/test/CodeGen/RISCV/double-frem.ll
M llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/double-intrinsics.ll
M llvm/test/CodeGen/RISCV/double-mem.ll
M llvm/test/CodeGen/RISCV/double-previous-failure.ll
M llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/double-round-conv.ll
M llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
M llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
M llvm/test/CodeGen/RISCV/emutls.ll
M llvm/test/CodeGen/RISCV/exception-pointer-register.ll
M llvm/test/CodeGen/RISCV/fastcc-float.ll
M llvm/test/CodeGen/RISCV/fastcc-int.ll
M llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/fli-licm.ll
M llvm/test/CodeGen/RISCV/float-arith-strict.ll
M llvm/test/CodeGen/RISCV/float-arith.ll
M llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
M llvm/test/CodeGen/RISCV/float-br-fcmp.ll
M llvm/test/CodeGen/RISCV/float-convert-strict.ll
M llvm/test/CodeGen/RISCV/float-convert.ll
M llvm/test/CodeGen/RISCV/float-fcmp-strict.ll
M llvm/test/CodeGen/RISCV/float-fcmp.ll
M llvm/test/CodeGen/RISCV/float-frem.ll
M llvm/test/CodeGen/RISCV/float-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/float-intrinsics.ll
M llvm/test/CodeGen/RISCV/float-mem.ll
M llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/float-round-conv.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/RISCV/float-zfa.ll
M llvm/test/CodeGen/RISCV/fmax-fmin.ll
M llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
M llvm/test/CodeGen/RISCV/forced-atomics.ll
M llvm/test/CodeGen/RISCV/fp128.ll
M llvm/test/CodeGen/RISCV/fp16-promote.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/frame-info.ll
M llvm/test/CodeGen/RISCV/frame.ll
M llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
M llvm/test/CodeGen/RISCV/ghccc-rv32.ll
M llvm/test/CodeGen/RISCV/ghccc-rv64.ll
M llvm/test/CodeGen/RISCV/ghccc-without-f-reg.ll
M llvm/test/CodeGen/RISCV/half-arith.ll
M llvm/test/CodeGen/RISCV/half-br-fcmp.ll
M llvm/test/CodeGen/RISCV/half-convert-strict.ll
M llvm/test/CodeGen/RISCV/half-convert.ll
M llvm/test/CodeGen/RISCV/half-frem.ll
M llvm/test/CodeGen/RISCV/half-intrinsics.ll
M llvm/test/CodeGen/RISCV/half-mem.ll
M llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
M llvm/test/CodeGen/RISCV/half-round-conv.ll
M llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
M llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
M llvm/test/CodeGen/RISCV/intrinsic-cttz-elts-vscale.ll
M llvm/test/CodeGen/RISCV/libcall-tail-calls.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/llvm.exp10.ll
M llvm/test/CodeGen/RISCV/llvm.frexp.ll
M llvm/test/CodeGen/RISCV/machine-outliner-and-machine-copy-propagation.ll
M llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
M llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
M llvm/test/CodeGen/RISCV/macro-fusion-lui-addi.ll
M llvm/test/CodeGen/RISCV/make-compressible.mir
M llvm/test/CodeGen/RISCV/mem.ll
M llvm/test/CodeGen/RISCV/mem64.ll
M llvm/test/CodeGen/RISCV/memcpy.ll
M llvm/test/CodeGen/RISCV/mir-target-flags.ll
M llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll
M llvm/test/CodeGen/RISCV/mul.ll
M llvm/test/CodeGen/RISCV/nest-register.ll
M llvm/test/CodeGen/RISCV/nomerge.ll
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
M llvm/test/CodeGen/RISCV/pr51206.ll
M llvm/test/CodeGen/RISCV/pr63816.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/reduce-unnecessary-extension.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rem.ll
M llvm/test/CodeGen/RISCV/remat.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
M llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
M llvm/test/CodeGen/RISCV/rv32xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rv64-large-stack.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/mem64.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
M llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
M llvm/test/CodeGen/RISCV/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64zbs.ll
M llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-llrint.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll
M llvm/test/CodeGen/RISCV/rvv/pr63596.ll
M llvm/test/CodeGen/RISCV/rvv/reg-alloc-reserve-bp.ll
M llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/select-and.ll
M llvm/test/CodeGen/RISCV/select-cc.ll
M llvm/test/CodeGen/RISCV/select-or.ll
M llvm/test/CodeGen/RISCV/setcc-logic.ll
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/shadowcallstack.ll
M llvm/test/CodeGen/RISCV/shifts.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/shrinkwrap-jump-table.ll
M llvm/test/CodeGen/RISCV/shrinkwrap.ll
M llvm/test/CodeGen/RISCV/split-sp-adjust.ll
M llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll
M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
M llvm/test/CodeGen/RISCV/srem-lkk.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/stack-protector-target.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/stack-slot-size.ll
M llvm/test/CodeGen/RISCV/stack-store-check.ll
M llvm/test/CodeGen/RISCV/tls-models.ll
M llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll
M llvm/test/CodeGen/RISCV/urem-lkk.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/CodeGen/RISCV/vector-abi.ll
M llvm/test/CodeGen/RISCV/vlenb.ll
M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
M llvm/test/CodeGen/RISCV/zcmp-with-float.ll
M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
M llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
A llvm/test/CodeGen/SPIRV/scfg-add-pre-headers.ll
M llvm/test/CodeGen/SystemZ/vec-perm-14.ll
M llvm/test/CodeGen/X86/O0-pipeline.ll
M llvm/test/CodeGen/X86/avx2-gather.ll
M llvm/test/CodeGen/X86/avx2-nontemporal.ll
M llvm/test/CodeGen/X86/combine-bextr.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-fast-isel-x86_64.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-x86.ll
M llvm/test/CodeGen/X86/crc32-intrinsics-x86_64.ll
M llvm/test/CodeGen/X86/evex-to-vex-compress.mir
M llvm/test/CodeGen/X86/ftrunc.ll
M llvm/test/CodeGen/X86/i64-mem-copy.ll
M llvm/test/CodeGen/X86/inline-sse.ll
M llvm/test/CodeGen/X86/invpcid-intrinsic.ll
M llvm/test/CodeGen/X86/lea-2.ll
M llvm/test/CodeGen/X86/legalize-shl-vec.ll
M llvm/test/CodeGen/X86/movdir-intrinsic-x86.ll
M llvm/test/CodeGen/X86/movdir-intrinsic-x86_64.ll
M llvm/test/CodeGen/X86/opt-pipeline.ll
M llvm/test/CodeGen/X86/sha.ll
M llvm/test/CodeGen/X86/test-shrink-bug.ll
M llvm/test/CodeGen/X86/vec_extract-avx.ll
M llvm/test/CodeGen/X86/vec_extract-mmx.ll
M llvm/test/CodeGen/X86/vec_extract-sse4.ll
M llvm/test/CodeGen/X86/vec_extract.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vector-lzcnt-256.ll
M llvm/test/CodeGen/X86/vector-shuffle-mmx.ll
M llvm/test/CodeGen/X86/vector-tzcnt-256.ll
M llvm/test/CodeGen/X86/x64-cet-intrinsics.ll
M llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
M llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll
M llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll
M llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll
M llvm/test/Instrumentation/AddressSanitizer/lifetime.ll
M llvm/test/Instrumentation/InstrProfiling/platform.ll
M llvm/test/Instrumentation/InstrProfiling/profiling.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
M llvm/test/MC/RISCV/function-call.s
M llvm/test/MC/RISCV/tail-call.s
M llvm/test/Other/print-at-pass-number.ll
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-signed.ll
M llvm/test/Transforms/InstCombine/icmp.ll
M llvm/test/Transforms/InstSimplify/select.ll
M llvm/test/Transforms/LoopVectorize/X86/drop-poison-generating-flags.ll
M llvm/test/Transforms/LoopVectorize/reduction-small-size.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
M llvm/test/Transforms/SCCP/switch.ll
A llvm/test/Transforms/SLPVectorizer/X86/splat-buildvector.ll
A llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll
M llvm/test/tools/dsymutil/ARM/dwarf5-dwarf4-combination-macho.test
M llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
M llvm/test/tools/llvm-dwarfdump/AArch64/verify-no-file.yaml
M llvm/unittests/Analysis/VectorFunctionABITest.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/utils/TableGen/CMakeLists.txt
A llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
R llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
M llvm/utils/TableGen/X86FoldTablesEmitter.cpp
A llvm/utils/TableGen/X86ManualCompressEVEXTables.def
M llvm/utils/gn/secondary/libcxx/src/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
M mlir/examples/toy/Ch6/toyc.cpp
M mlir/examples/toy/Ch7/toyc.cpp
A mlir/include/mlir/Analysis/Presburger/Barvinok.h
A mlir/include/mlir/Analysis/Presburger/GeneratingFunction.h
M mlir/include/mlir/Analysis/Presburger/IntegerRelation.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/BufferUtils.h
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/include/mlir/Dialect/LLVMIR/Transforms/Passes.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVAtomicOps.td
M mlir/include/mlir/Dialect/SPIRV/IR/SPIRVStructureOps.td
M mlir/include/mlir/ExecutionEngine/RunnerUtils.h
M mlir/include/mlir/IR/Dominance.h
M mlir/include/mlir/Interfaces/ControlFlowInterfaces.td
A mlir/lib/Analysis/Presburger/Barvinok.cpp
M mlir/lib/Analysis/Presburger/CMakeLists.txt
R mlir/lib/Analysis/Presburger/GeneratingFunction.h
M mlir/lib/Analysis/Presburger/IntegerRelation.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp
M mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
M mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferOptimizations.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferUtils.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferViewFlowAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/EmptyTensorElimination.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/KernelOutlining.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMInlining.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/DIScopeForLLVMFuncOp.cpp
M mlir/lib/Dialect/SPIRV/IR/AtomicOps.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp
M mlir/lib/Interfaces/ControlFlowInterfaces.cpp
M mlir/lib/Target/LLVMIR/DebugImporter.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp
M mlir/lib/Target/SPIRV/Deserialization/Deserializer.h
M mlir/lib/Target/SPIRV/Serialization/SerializeOps.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.cpp
M mlir/lib/Target/SPIRV/Serialization/Serializer.h
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/python/mlir/ir.py
M mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir
M mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
M mlir/test/Conversion/MemRefToSPIRV/atomic.mlir
M mlir/test/Conversion/MemRefToSPIRV/bitwidth-emulation.mlir
M mlir/test/Conversion/SCFToGPU/no_blocks_no_threads.mlir
M mlir/test/Conversion/SPIRVToLLVM/spirv-storage-class-mapping.mlir
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/outlining.mlir
M mlir/test/Dialect/LLVMIR/add-debuginfo-func-scope.mlir
M mlir/test/Dialect/LLVMIR/call-location.mlir
M mlir/test/Dialect/LLVMIR/debuginfo.mlir
M mlir/test/Dialect/LLVMIR/global.mlir
M mlir/test/Dialect/LLVMIR/inlining.mlir
M mlir/test/Dialect/LLVMIR/invalid-call-location.mlir
M mlir/test/Dialect/LLVMIR/loop-metadata.mlir
M mlir/test/Dialect/LLVMIR/mem2reg-dbginfo.mlir
M mlir/test/Dialect/SPIRV/IR/atomic-ops.mlir
M mlir/test/Dialect/SPIRV/IR/availability.mlir
M mlir/test/Dialect/SPIRV/IR/cast-ops.mlir
M mlir/test/Dialect/SPIRV/IR/function-decorations.mlir
M mlir/test/Dialect/SPIRV/IR/target-env.mlir
M mlir/test/Dialect/SPIRV/Transforms/inlining.mlir
M mlir/test/Dialect/SPIRV/Transforms/vce-deduction.mlir
M mlir/test/Target/LLVMIR/Import/debug-info.ll
M mlir/test/Target/LLVMIR/Import/global-variables.ll
M mlir/test/Target/LLVMIR/llvmir-debug.mlir
M mlir/test/Target/LLVMIR/loop-metadata.mlir
M mlir/test/Target/SPIRV/atomic-ops.mlir
M mlir/test/Target/SPIRV/cast-ops.mlir
M mlir/test/Target/SPIRV/debug.mlir
M mlir/test/Target/SPIRV/function-decorations.mlir
M mlir/test/Transforms/canonicalize.mlir
M mlir/test/python/dialects/memref.py
A mlir/unittests/Analysis/Presburger/BarvinokTest.cpp
M mlir/unittests/Analysis/Presburger/CMakeLists.txt
A mlir/unittests/Analysis/Presburger/GeneratingFunctionTest.cpp
M mlir/unittests/Analysis/Presburger/IntegerRelationTest.cpp
M mlir/unittests/Analysis/Presburger/Utils.h
M openmp/CMakeLists.txt
M openmp/cmake/OpenMPTesting.cmake
M openmp/libomptarget/plugins-nextgen/amdgpu/CMakeLists.txt
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
M openmp/libomptarget/plugins-nextgen/amdgpu/utils/UtilitiesRTL.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/runtime/CMakeLists.txt
M openmp/runtime/cmake/LibompGetArchitecture.cmake
M openmp/runtime/cmake/config-ix.cmake
M openmp/runtime/src/CMakeLists.txt
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_config.h.cmake
M openmp/runtime/src/kmp_ftn_entry.h
M openmp/runtime/src/kmp_global.cpp
M openmp/runtime/src/kmp_gsupport.cpp
M openmp/runtime/src/kmp_os.h
M openmp/runtime/src/kmp_platform.h
M openmp/runtime/src/kmp_runtime.cpp
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_wrapper_getpid.h
M openmp/runtime/src/z_Linux_util.cpp
M openmp/runtime/test/lit.cfg
M polly/lib/Transform/ScheduleOptimizer.cpp
A polly/test/ScheduleOptimizer/schedule_computeout.ll
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
optional unwind
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/6496ace3246f...4301f9aa15dd
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