[all-commits] [llvm/llvm-project] d460c1: [DAG] SimplifyDemandedBits - don't fold sext(x) ->...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d460c1de3b989cea919b9d60c21644f28f987950
      https://github.com/llvm/llvm-project/commit/d460c1de3b989cea919b9d60c21644f28f987950
  Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
  Date:   2024-01-08 (Mon, 08 Jan 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-zip.ll
    M llvm/test/CodeGen/AArch64/vselect-ext.ll
    M llvm/test/CodeGen/SystemZ/vec-perm-14.ll
    M llvm/test/CodeGen/X86/test-shrink-bug.ll
    M llvm/test/CodeGen/X86/vec_setcc.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - don't fold sext(x) -> aext(x) if we lose an 0/-1 allsignbits mask (#77296)

For targets that use 0/-1 boolean results, we want to keep this pattern through extensions/truncations as much as possible - so avoid simplifying to any_extend even if we don't demand the upper bits.

Noticed in triage for https://reviews.llvm.org/D152928