[all-commits] [llvm/llvm-project] 780a51: [AArch64] Fix condition for combining UADDV and Ad...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 780a5116ba68ec8c53b65008b3407479478b2d5e
      https://github.com/llvm/llvm-project/commit/780a5116ba68ec8c53b65008b3407479478b2d5e
  Author: David Green <david.green at arm.com>
  Date:   2024-01-07 (Sun, 07 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64] Fix condition for combining UADDV and Add. (#76809)

This should have been checking that the transform was valid, but used
incorrect conditions letting through invalid combinations of lo/hi
extracts.

Hopefully fixes #76769