[all-commits] [llvm/llvm-project] 06f1e1: [mlir][nvvm] Add clock and clock64 special registe...

[Guray Ozen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 06f1e10908e624c1e90a0c647e9f74826ad3f011
      https://github.com/llvm/llvm-project/commit/06f1e10908e624c1e90a0c647e9f74826ad3f011
  Author: Guray Ozen <guray.ozen at gmail.com>
  Date:   2024-01-05 (Fri, 05 Jan 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
    M mlir/test/Target/LLVMIR/nvvmir.mlir

  Log Message:
  -----------
  [mlir][nvvm] Add clock and clock64 special registers (#77088)

Tihs PR adds `clock` and `clock64` special registers to NVVM dialect.