[all-commits] [llvm/llvm-project] ace69e: [mlir][gpu] Improve `gpu-lower-to-nvvm-pipeline` D...

[Guray Ozen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ace69e6b942b8fa7e610d70be2a92e801ceea481
      https://github.com/llvm/llvm-project/commit/ace69e6b942b8fa7e610d70be2a92e801ceea481
  Author: Guray Ozen <guray.ozen at gmail.com>
  Date:   2024-01-05 (Fri, 05 Jan 2024)

  Changed paths:
    M mlir/docs/Dialects/GPU.md
    M mlir/include/mlir/Dialect/GPU/Pipelines/Passes.h
    M mlir/lib/Dialect/GPU/Pipelines/GPUToNVVMPipeline.cpp
    M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/dump-ptx.mlir
    M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir
    M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir
    M mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f16-f16-accum.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/sm80/transform-mma-sync-matmul-f32.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32-bare-ptr.mlir
    M mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-and.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-maxsi.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-minsi.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-op.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-or.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-region.mlir
    M mlir/test/Integration/GPU/CUDA/all-reduce-xor.mlir
    M mlir/test/Integration/GPU/CUDA/gpu-to-cubin.mlir
    M mlir/test/Integration/GPU/CUDA/multiple-all-reduce.mlir
    M mlir/test/Integration/GPU/CUDA/printf.mlir
    M mlir/test/Integration/GPU/CUDA/shuffle.mlir
    A mlir/test/Integration/GPU/CUDA/sm90/asd
    M mlir/test/Integration/GPU/CUDA/sm90/cga_cluster.mlir
    M mlir/test/Integration/GPU/CUDA/sm90/gemm_f32_f16_f16_128x128x128.mlir
    M mlir/test/Integration/GPU/CUDA/sm90/gemm_pred_f32_f16_f16_128x128x128.mlir
    M mlir/test/Integration/GPU/CUDA/sm90/tma_load_128x64_swizzle128b.mlir
    M mlir/test/Integration/GPU/CUDA/sm90/tma_load_64x64_swizzle128b.mlir
    M mlir/test/Integration/GPU/CUDA/sm90/tma_load_64x8_8x128_noswizzle.mlir
    M mlir/test/Integration/GPU/CUDA/two-modules.mlir

  Log Message:
  -----------
  [mlir][gpu] Improve `gpu-lower-to-nvvm-pipeline` Documentation (#77062)

This PR improves the documentation for the `gpu-lower-to-nvvm-pipeline`
(as it was remaning item for #75775)

- Changes pipeline `gpu-lower-to-nvvm` -> `gpu-lower-to-nvvm-pipeline`
- Adds a section in GPU Dialect in website. It clarifies the pipeline's
functionality in lowering primary dialects to NVVM targets.