[all-commits] [llvm/llvm-project] 58f164: [RISCV][llvm-mca] Use correct LMUL and SEW for str...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 58f1640635feff282935153d295dfb4ea1818401
      https://github.com/llvm/llvm-project/commit/58f1640635feff282935153d295dfb4ea1818401
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-01-04 (Thu, 04 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-store.s

  Log Message:
  -----------
  [RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869)

The pseudos for strided loads and stores use the SEW coming from the
name. For example, vlse8 has SEW=8 and vlse16 has SEW=16.

When llvm-mca tries to lookup (VLSE8_V, SEW=S, LMUL=L) in the inverse
pseudo table, a result will only be found when S=8, where S was set from
the previous vsetvli instruction. Instead, for a match to be found, we
must lookup (VLSE8_V, SEW=8, LMUL=L') where L' is the EMUL which was
calculated by scaling the LMUL and SEW from the previous vsetvli and the
SEW=8.