[all-commits] [llvm/llvm-project] 09de5e: [Clang] Fix failing CI with different test case at...
Amir Ayupov via All-commits
all-commits at lists.llvm.org
Thu Jan 4 07:39:20 PST 2024
Branch: refs/heads/users/aaupov/spr/bolt-delta-encode-function-start-addresses-in-bat
Home: https://github.com/llvm/llvm-project
Commit: 09de5e5c6d8c25fe76840c69056afca72275dd6b
https://github.com/llvm/llvm-project/commit/09de5e5c6d8c25fe76840c69056afca72275dd6b
Author: Yuxuan Chen <yuxuanchen1997 at outlook.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M clang/test/SemaCXX/template-instantiation.cpp
Log Message:
-----------
[Clang] Fix failing CI with different test case attribute & host triple (#76863)
As in title,
https://github.com/llvm/llvm-project/commit/a8f43974260ec244d78336d2530f8fc097753580
broke CI due to the calling convention not available on certain targets.
This patch uses a simpler calling convention and enables the test only
when the attribute exists. It's verified that this test crashes the
compiler before a8f43974260ec244d78336d2530f8fc097753580 so it's the
same effect as the previous test. Disabling the test on platforms that
don't have the calling convention is fine because it's guarding against
a frontend bug.
Commit: 49029f926d359075d59ad4aec2d01a21d9514b02
https://github.com/llvm/llvm-project/commit/49029f926d359075d59ad4aec2d01a21d9514b02
Author: Alex Langford <alangford at apple.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M lldb/source/Breakpoint/BreakpointResolverAddress.cpp
M lldb/test/API/functionalities/breakpoint/serialize/TestBreakpointSerialization.py
Log Message:
-----------
[lldb] Fix breakpoint resolver serialization bug (#76766)
BreakpointResolverAddress optionally can include the module name related
to the address that gets resolved. Currently this will never work
because it sets the name to itself (which is empty).
Commit: 49b492048af2b2093aaed899c0bbd6d740aad83c
https://github.com/llvm/llvm-project/commit/49b492048af2b2093aaed899c0bbd6d740aad83c
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/AMDGPU/literalv216.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt
Log Message:
-----------
AMDGPU: Fix packed 16-bit inline constants (#76522)
Consistently treat packed 16-bit operands as 32-bit values, because
that's really what they are. The attempt to treat them differently was
ultimately incorrect and lead to miscompiles, e.g. when using non-splat
constants such as (1, 0) as operands.
Recognize 32-bit float constants for i/u16 instructions. This is a bit
odd conceptually, but it matches HW behavior and SP3.
Remove isFoldableLiteralV216; there was too much magic in the dependency
between it and its use in SIFoldOperands. Instead, we now simply rely on
checking whether a constant is an inline constant, and trying a bunch of
permutations of the low and high halves. This is more obviously correct
and leads to some new cases where inline constants are used as shown by
tests.
Move the logic for switching packed add vs. sub into SIFoldOperands.
This has two benefits: all logic that optimizes for inline constants in
packed math is now in one place; and it applies to both SelectionDAG and
GISel paths.
Disable the use of opsel with v_dot* instructions on gfx11. They are
documented to ignore opsel on src0 and src1. It may be interesting to
re-enable to use of opsel on src2 as a future optimization.
A similar "proper" fix of what inline constants mean could potentially
be applied to unpacked 16-bit ops. However, it's less clear what the
benefit would be, and there are surely places where we'd have to
carefully audit whether values are properly sign- or zero-extended. It
is best to keep such a change separate.
Fixes: Corruption in FSR 2.0 (latent bug exposed by an LLPC change)
Commit: 3f2e670671e718579cf98f1bf0087b6d0ee4919c
https://github.com/llvm/llvm-project/commit/3f2e670671e718579cf98f1bf0087b6d0ee4919c
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp
Log Message:
-----------
Revert "[Clang][Sema] Diagnose unexpanded packs in the template argument lists of function template specializations" (#76876)
Reverts llvm/llvm-project#76677
See discussion here: https://github.com/llvm/llvm-project/pull/76677
Commit: a25b66217f41564f933dd1d6d2993d990615c47b
https://github.com/llvm/llvm-project/commit/a25b66217f41564f933dd1d6d2993d990615c47b
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-exegesis/lib/Assembler.h
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h
Log Message:
-----------
[NFC][llvm-exegesis] Remove redundant register initial values argument
This patch removes the redundant RegisterInitialValues parameter from
assembleToStream and friends as it is included within the BenchmarkKey
struct that is also passed to all the functions that need this
information.
Commit: 428cf71ffa01c579e0ebf66b7d74eb9cb8d8f3f8
https://github.com/llvm/llvm-project/commit/428cf71ffa01c579e0ebf66b7d74eb9cb8d8f3f8
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/tools/llvm-nm/wasm/linked.yaml
A llvm/test/tools/llvm-objdump/wasm/linked-symbol-table.yaml
Log Message:
-----------
Reland "[WebAssembly][Object]Use file offset as function symbol address for linked files (#76198)"
WebAssembly doesn't have a single virtual memory space the way other object
formats or architectures do, so "addresses" mean different things depending
on the context.
Function symbol addresses in object files are offsets from the start of the code
section. This is good for linking and relocation. However when dealing with
linked binaries, offsets from the start of the file/module are more often
used (e.g. for stack traces in browsers), and are more useful for use
cases like binary size attribution. This PR changes Object to use
the file offset instead of the section offset for function symbols, but
only for linked (non-DSO) files.
This is a reland of fc5f51cf with a fix for the MSan failure (it was not caused
by this change, but it was revealed by the new tests).
Commit: 7a4c49756db161ebcce08c7bc860a569aad7f276
https://github.com/llvm/llvm-project/commit/7a4c49756db161ebcce08c7bc860a569aad7f276
Author: Boian Petkantchin <boian.petkantchin at amd.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Mesh/IR/MeshBase.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
Log Message:
-----------
[mlir][mesh] Use one type for mesh axis (#76830)
Make all ops and attributes use the types MeshAxis and MeshAxesAttr
instead of int16_t, int32_t, DenseI16ArrayAttr and DenseI32ArrayAttr.
Commit: e68a0320a1592bf408ac6458efa2d1c548cfed7a
https://github.com/llvm/llvm-project/commit/e68a0320a1592bf408ac6458efa2d1c548cfed7a
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M libc/src/signal/linux/signal_utils.h
Log Message:
-----------
[libc] fix -Wcast-function-type via union rather than reinterpret_cast (#76875)
The GCC build is producing the following diagnostic:
llvm-project/libc/src/signal/linux/signal_utils.h: In member function
‘__llvm_libc_18_0_0_git::KernelSigaction&
__llvm_libc_18_0_0_git::KernelSigaction::operator=(const sigaction&)’:
llvm-project/libc/src/signal/linux/signal_utils.h:38:20: warning:
cast between incompatible function types from ‘void (*)(int, siginfo_t*,
void*)’ to ‘void (*)(int)’ [-Wcast-function-type]
38 | sa_handler = reinterpret_cast<HandlerType *>(sa.sa_sigaction);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
llvm-project/libc/src/signal/linux/signal_utils.h: In member function
‘__llvm_libc_18_0_0_git::KernelSigaction::operator sigaction() const’:
llvm-project/libc/src/signal/linux/signal_utils.h:51:25: warning:
cast between incompatible function types from ‘void (*)(int)’ to ‘void
(*)(int, siginfo_t*, void*)’ [-Wcast-function-type]
51 | sa.sa_sigaction = reinterpret_cast<SiginfoHandlerType
*>(sa_handler);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Two issues here:
1. Clang supports -Wcast-function-type, but not as part of the -Wextra
group.
2. The existing implementation tried to work around the oddity that is
the
kernel's struct sigaction != POSIX via reinterpret_cast in a way that's
not
compatible with -Wcast-function-type. Just use a union which is well
defined
(and two function pointers are the same size.)
Link: https://github.com/llvm/llvm-project/issues/76872
Fixes: https://github.com/llvm/llvm-project/issues/74617
Commit: bdaedffc43a608ef5fdc8a0e0c524be0a3a8f72e
https://github.com/llvm/llvm-project/commit/bdaedffc43a608ef5fdc8a0e0c524be0a3a8f72e
Author: Alex Langford <alangford at apple.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M lldb/test/API/functionalities/breakpoint/serialize/TestBreakpointSerialization.py
Log Message:
-----------
[lldb] Speculatively fix TestBreakpointSerialization on Windows
See: https://lab.llvm.org/buildbot/#/builders/219/builds/7961/steps/6/logs/stdio
Commit: ddfbca8b08941125b48039236a03635252298611
https://github.com/llvm/llvm-project/commit/ddfbca8b08941125b48039236a03635252298611
Author: YunQiang Su <wzssyqa at gmail.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Arch/Mips.cpp
M clang/test/Driver/mips-features.c
Log Message:
-----------
Clang/MIPS: Use -mnan value for -mabs if not specified (#71157)
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008.
Let's use this behaivor by default.
With this commit, `clang -target mips -mnan=2008 -c fabs.c` will imply
`-mabs=2008`.
And of course, `clang -mnan=2008 -mabs=legacy` can continue workable
like previous.
Co-authored-by: YunQiang Su <yunqiang.su at cipunited.com>
Commit: 7df28fd61aa4603846b3ce16f9f988ccc780a584
https://github.com/llvm/llvm-project/commit/7df28fd61aa4603846b3ce16f9f988ccc780a584
Author: Micah Weston <micahsweston at gmail.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M llvm/docs/Extensions.rst
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll
A llvm/test/CodeGen/X86/basic-block-sections-labels-pgo-features.ll
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP][AsmPrinter] Implements PGOAnalysisMap emitting in AsmPrinter with tests. (#75202)
Uses machine analyses to emit PGOAnalysisMap into the bb-addr-map ELF
section. Implements filecheck tests to verify emitting new fields.
This patch emits optional PGO related analyses into the bb-addr-map ELF
section during AsmPrinter. This currently supports Function Entry Count,
Machine Block Frequencies. and Machine Branch Probabilities. Each is
independently enabled via the `feature` byte of `bb-addr-map` for the given
function.
A part of [RFC - PGO Accuracy Metrics: Emitting and Evaluating Branch and Block Analysis](https://discourse.llvm.org/t/rfc-pgo-accuracy-metrics-emitting-and-evaluating-branch-and-block-analysis/73902).
Commit: dd9681f839c23e9caa6c495fb5a0df3625715348
https://github.com/llvm/llvm-project/commit/dd9681f839c23e9caa6c495fb5a0df3625715348
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrUtils.td
A llvm/test/MC/Disassembler/X86/apx/adx.txt
A llvm/test/MC/Disassembler/X86/apx/dec.txt
A llvm/test/MC/Disassembler/X86/apx/inc.txt
A llvm/test/MC/X86/apx/adx-att.s
A llvm/test/MC/X86/apx/adx-intel.s
A llvm/test/MC/X86/apx/dec-att.s
A llvm/test/MC/X86/apx/dec-intel.s
A llvm/test/MC/X86/apx/inc-att.s
A llvm/test/MC/X86/apx/inc-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][MC] Support encoding/decoding for APX variant INC/DEC/ADCX/ADOX instructions (#76721)
Four variants: promoted legacy, ND (new data destination), NF (no flags
update) and NF_ND (NF + ND).
The syntax of NF instructions is aligned with GNU binutils.
https://sourceware.org/pipermail/binutils/2023-September/129545.html
Commit: ddf0096a92e4c2852fd57321f02cbd78e596943c
https://github.com/llvm/llvm-project/commit/ddf0096a92e4c2852fd57321f02cbd78e596943c
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/test/MC/Disassembler/X86/apx/amx-tile.txt
A llvm/test/MC/Disassembler/X86/apx/bmi2.txt
A llvm/test/MC/Disassembler/X86/apx/cet.txt
M llvm/test/MC/Disassembler/X86/apx/cmpccxadd.txt
R llvm/test/MC/Disassembler/X86/apx/invept.txt
M llvm/test/MC/Disassembler/X86/apx/invpcid.txt
R llvm/test/MC/Disassembler/X86/apx/invvpid.txt
M llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
M llvm/test/MC/Disassembler/X86/apx/movdiri.txt
R llvm/test/MC/Disassembler/X86/apx/mulx.txt
R llvm/test/MC/Disassembler/X86/apx/rorx.txt
R llvm/test/MC/Disassembler/X86/apx/sarx.txt
A llvm/test/MC/Disassembler/X86/apx/sha.txt
R llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
R llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
R llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
R llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
R llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
R llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
R llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
R llvm/test/MC/Disassembler/X86/apx/shlx.txt
R llvm/test/MC/Disassembler/X86/apx/shrx.txt
A llvm/test/MC/Disassembler/X86/apx/vmx.txt
R llvm/test/MC/Disassembler/X86/apx/wrssd.txt
R llvm/test/MC/Disassembler/X86/apx/wrssq.txt
R llvm/test/MC/Disassembler/X86/apx/wrussd.txt
R llvm/test/MC/Disassembler/X86/apx/wrussq.txt
M llvm/test/MC/X86/apx/amx-tile-att.s
M llvm/test/MC/X86/apx/amx-tile-intel.s
A llvm/test/MC/X86/apx/bmi2-att.s
A llvm/test/MC/X86/apx/bmi2-intel.s
A llvm/test/MC/X86/apx/cet-att.s
A llvm/test/MC/X86/apx/cet-intel.s
M llvm/test/MC/X86/apx/cmpccxadd-att.s
M llvm/test/MC/X86/apx/cmpccxadd-intel.s
R llvm/test/MC/X86/apx/invept-att.s
R llvm/test/MC/X86/apx/invept-intel.s
M llvm/test/MC/X86/apx/invpcid-att.s
M llvm/test/MC/X86/apx/invpcid-intel.s
R llvm/test/MC/X86/apx/invvpid-att.s
R llvm/test/MC/X86/apx/invvpid-intel.s
M llvm/test/MC/X86/apx/movdir64b-att.s
M llvm/test/MC/X86/apx/movdir64b-intel.s
M llvm/test/MC/X86/apx/movdiri-att.s
M llvm/test/MC/X86/apx/movdiri-intel.s
R llvm/test/MC/X86/apx/mulx-att.s
R llvm/test/MC/X86/apx/mulx-intel.s
R llvm/test/MC/X86/apx/pdep-att.s
R llvm/test/MC/X86/apx/pdep-intel.s
R llvm/test/MC/X86/apx/pext-att.s
R llvm/test/MC/X86/apx/pext-intel.s
R llvm/test/MC/X86/apx/rorx-att.s
R llvm/test/MC/X86/apx/rorx-intel.s
R llvm/test/MC/X86/apx/sarx-att.s
R llvm/test/MC/X86/apx/sarx-intel.s
A llvm/test/MC/X86/apx/sha-att.s
A llvm/test/MC/X86/apx/sha-intel.s
R llvm/test/MC/X86/apx/sha1msg1-att.s
R llvm/test/MC/X86/apx/sha1msg1-intel.s
R llvm/test/MC/X86/apx/sha1msg2-att.s
R llvm/test/MC/X86/apx/sha1msg2-intel.s
R llvm/test/MC/X86/apx/sha1nexte-att.s
R llvm/test/MC/X86/apx/sha1nexte-intel.s
R llvm/test/MC/X86/apx/sha1rnds4-att.s
R llvm/test/MC/X86/apx/sha1rnds4-intel.s
R llvm/test/MC/X86/apx/sha256msg1-att.s
R llvm/test/MC/X86/apx/sha256msg1-intel.s
R llvm/test/MC/X86/apx/sha256msg2-att.s
R llvm/test/MC/X86/apx/sha256msg2-intel.s
R llvm/test/MC/X86/apx/sha256rnds2-att.s
R llvm/test/MC/X86/apx/sha256rnds2-intel.s
R llvm/test/MC/X86/apx/shlx-att.s
R llvm/test/MC/X86/apx/shlx-intel.s
R llvm/test/MC/X86/apx/shrx-att.s
R llvm/test/MC/X86/apx/shrx-intel.s
A llvm/test/MC/X86/apx/vmx-att.s
A llvm/test/MC/X86/apx/vmx-intel.s
R llvm/test/MC/X86/apx/wrssd-att.s
R llvm/test/MC/X86/apx/wrssd-intel.s
R llvm/test/MC/X86/apx/wrssq-att.s
R llvm/test/MC/X86/apx/wrssq-intel.s
R llvm/test/MC/X86/apx/wrussd-att.s
R llvm/test/MC/X86/apx/wrussd-intel.s
R llvm/test/MC/X86/apx/wrussq-att.s
R llvm/test/MC/X86/apx/wrussq-intel.s
Log Message:
-----------
[NFC][X86] Reorg MC tests for APX promoted instrs (#76697)
As suggested in https://github.com/llvm/llvm-project/pull/76210, this
patch re-organize the mc tests for apx promoted instrs, instr tests
within same cpuid would be listed in one test.
Also add explicit prefix {evex} tests and 8 displacement memory test,
promoted instrs need set No_CD8 to avoid AVX512 compress encoding.
Commit: 53edf12e526704cc251b6a6917319c7cb7a653a0
https://github.com/llvm/llvm-project/commit/53edf12e526704cc251b6a6917319c7cb7a653a0
Author: Jerry Wu <cheyuw at google.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/unittests/Dialect/CMakeLists.txt
A mlir/unittests/Dialect/Linalg/CMakeLists.txt
A mlir/unittests/Dialect/Linalg/LinalgInterfacesTest.cpp
Log Message:
-----------
[mlir] Add `res()` method to `linalg::ContractionOpInterface` (#76539)
In addition to `lhs()` and `rhs()` to return left and right operands,
add `res()` to return the result value.
Commit: cda388c4407e0fe42faa82c015ee77da160ebd25
https://github.com/llvm/llvm-project/commit/cda388c4407e0fe42faa82c015ee77da160ebd25
Author: Mircea Trofin <mtrofin at google.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M llvm/test/CodeGen/MLRegAlloc/dev-mode-extra-features-logging.ll
Log Message:
-----------
[mlgo] Fix test post PR #76697
Opcode values changed, trivial fix.
Commit: 6ae7f66ff5169ddc5a7b9ab545707042c77e036c
https://github.com/llvm/llvm-project/commit/6ae7f66ff5169ddc5a7b9ab545707042c77e036c
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M mlir/CMakeLists.txt
M mlir/examples/minimal-opt/README.md
M mlir/include/mlir/Config/mlir-config.h.cmake
M mlir/include/mlir/Conversion/LLVMCommon/TypeConverter.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.h
A mlir/include/mlir/IR/PDLPatternMatch.h.inc
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/ComplexToLibm/CMakeLists.txt
M mlir/lib/Conversion/MathToLibm/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/TransformOps/CMakeLists.txt
M mlir/lib/IR/CMakeLists.txt
A mlir/lib/IR/PDL/PDLPatternMatch.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Rewrite/ByteCode.h
M mlir/lib/Rewrite/CMakeLists.txt
M mlir/lib/Rewrite/FrozenRewritePatternSet.cpp
M mlir/lib/Rewrite/PatternApplicator.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/CMakeLists.txt
M mlir/test/lib/Rewrite/CMakeLists.txt
M mlir/test/lib/Tools/PDLL/CMakeLists.txt
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/tools/mlir-lsp-server/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir] Add config for PDL (#69927)
Make it so that PDL in pattern rewrites can be optionally disabled.
PDL is still enabled by default and not optional bazel. So this should
be a NOP for most folks, while enabling other to disable.
This only works with tests disabled. With tests enabled this still
compiles but tests fail as there is no lit config to disable tests that
depend on PDL rewrites yet.
Commit: 42ec976184acd40436acd7104ad715c60ca3e7ed
https://github.com/llvm/llvm-project/commit/42ec976184acd40436acd7104ad715c60ca3e7ed
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M clang/docs/ClangFormat.rst
M clang/test/Format/clang-format-ignore.cpp
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
[clang-format] Optimize processing .clang-format-ignore files (#76733)
Reuse the patterns governing the previous input file being formatted if
the current input file is from the same directory.
Commit: 80889ae0297453476f600d6a8cf776f272dac461
https://github.com/llvm/llvm-project/commit/80889ae0297453476f600d6a8cf776f272dac461
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-03 (Wed, 03 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Log Message:
-----------
[RISCV] Remove RISCVISD::VSELECT_VL. (#76866)
We can use RISCVISD::VMERGE_VL with an undef passthru operand.
I had to rewrite the FMA patterns to handle both undef and non-undef
cases so we can get the tail policy.
Commit: 0ce193708cb682f3ad742ad909d8a5346a505ac7
https://github.com/llvm/llvm-project/commit/0ce193708cb682f3ad742ad909d8a5346a505ac7
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
Log Message:
-----------
[InstCombine] Refactor folding of commutative binops over select/phi/minmax (#76692)
This patch cleans up the duplicate code for folding commutative binops
over `select/phi/minmax`.
Related commits:
+ select support:
https://github.com/llvm/llvm-project/commit/88cc35b27e6c7966ab2463fa06d3dd970e88df64
+ phi support:
https://github.com/llvm/llvm-project/commit/8674a023bcacb677ce48b8831e2ae35b5aa2d8ef
+ minmax support:
https://github.com/llvm/llvm-project/commit/624973806c5644ccfa84805319b5852edb68d48d
Commit: cd28da390f8b8dedd00f9a2a383ec81e90436841
https://github.com/llvm/llvm-project/commit/cd28da390f8b8dedd00f9a2a383ec81e90436841
Author: Nilanjana Basu <n_basu at apple.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
Log Message:
-----------
[LV] Change loops' interleave count computation (#73766)
[LV] Change loops' interleave count computation
A set of microbenchmarks in llvm-test-suite (https://github.com/llvm/llvm-test-suite/pull/56), when tested on a AArch64 platform, demonstrates that loop interleaving is beneficial when the vector loop runs at least twice or when the epilogue loop trip count (TC) is minimal. Therefore, we choose interleaving count (IC) between TC/VF & TC/2*VF (VF = vectorization factor), such that remainder TC for the epilogue loop is minimum while the IC is maximum in case the remainder TC is same for both.
The initial tests for this change were submitted in PRs:
https://github.com/llvm/llvm-project/pull/70272 and https://github.com/llvm/llvm-project/pull/74689.
Commit: 55395f5c8375d3fce1ccbf0ab75f3539c56d61c7
https://github.com/llvm/llvm-project/commit/55395f5c8375d3fce1ccbf0ab75f3539c56d61c7
Author: sstipanovic <146831748+sstipanovic at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
A llvm/test/CodeGen/AMDGPU/image-atomic-attributes.ll
Log Message:
-----------
[AMDGPU] Remove `nosync` from image atomic intrinsics. (#76814)
Remove `nosync` as discussed in
https://github.com/llvm/llvm-project/pull/73613
Commit: 5550e9c841465c54c6f28e246d835daf3520a2ca
https://github.com/llvm/llvm-project/commit/5550e9c841465c54c6f28e246d835daf3520a2ca
Author: David Green <david.green at arm.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/fpowi.ll
Log Message:
-----------
[GlobalISel][AArch64] Add libcall lowering for fpowi. (#67114)
This adds legalization, notably libcall lowering for fpowi. It is a
little different to other methods as the function takes both a float and
integer register. Otherwise all vectors get scalarized and fp16 is
promoted to fp32.
Commit: 176c341198cbfa05debc3554e958ea90e0ef3cc9
https://github.com/llvm/llvm-project/commit/176c341198cbfa05debc3554e958ea90e0ef3cc9
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/bfloat.ll
Log Message:
-----------
[X86][BF16] Add 32-bit tests to show ABI problem, NFC
Commit: 0cdaadf15aaa6609f93e3508417b47baa3891996
https://github.com/llvm/llvm-project/commit/0cdaadf15aaa6609f93e3508417b47baa3891996
Author: Dominik Adamski <dominik.adamski at amd.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M openmp/libomptarget/test/lit.cfg
Log Message:
-----------
[libomptarget][flang] Explicitly pass the OpenMP device libraries to tests (#76796)
This pull request is a follow-up of patch:
https://github.com/llvm/llvm-project/pull/68225 and it explicitly
specifies OpenMP device libraries for Fortran OpenMP tests.
Commit: 75365b2e189a54b96a907ebe327c5898dd7aad14
https://github.com/llvm/llvm-project/commit/75365b2e189a54b96a907ebe327c5898dd7aad14
Author: Ben Shi <2283975856 at qq.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/AVR.h
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
Log Message:
-----------
[clang][AVR] Restrict range of assembly constraint 'G' (#76561)
According to
https://www.nongnu.org/avr-libc/user-manual/inline_asm.html, 'G' only
represents floating point constant '0.0'. And avr-gcc also rejects other
non-zero FP values.
Commit: 18c0f59b3eeed880384aa37c7feca2064b994f37
https://github.com/llvm/llvm-project/commit/18c0f59b3eeed880384aa37c7feca2064b994f37
Author: Ben Shi <2283975856 at qq.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/stream-error.c
M clang/test/Analysis/stream-non-posix-function.c
M clang/test/Analysis/stream-note.c
M clang/test/Analysis/stream-stdlibraryfunctionargs.c
M clang/test/Analysis/stream.c
Log Message:
-----------
[clang][analyzer] Support 'fdopen' in the StreamChecker (#76776)
Commit: 8c72ff716b3e4b298695fa3faf6add860c6dbcb2
https://github.com/llvm/llvm-project/commit/8c72ff716b3e4b298695fa3faf6add860c6dbcb2
Author: bgra8 <32298056+bgra8 at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M libcxx/include/__format/format_arg_store.h
M libcxx/test/libcxx/system_reserved_names.gen.py
Log Message:
-----------
[NFC] Renames a template parameter to avoid clashes with userspace names. (#76829)
Co-authored-by: Bogdan Graur <bgraur at google.com>
Commit: f3f4387e02b0ed637b5d843e8937116334329a65
https://github.com/llvm/llvm-project/commit/f3f4387e02b0ed637b5d843e8937116334329a65
Author: gmh <13917777+gmh5225 at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.cpp
M lldb/unittests/Thread/ThreadTest.cpp
Log Message:
-----------
[lldb][NFC] Fix compilation issue on windows (#76453)
Commit: 232be5129b205b0eefee52b7ff930d597298bbfc
https://github.com/llvm/llvm-project/commit/232be5129b205b0eefee52b7ff930d597298bbfc
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
Log Message:
-----------
[NFC][llvm-exegesis] Fix comment text
I'm reasonably confident iff wasn't an abbreviation for if and only if
here and it was starting to bug me quite a bit.
Commit: f8c034140b577c81ddaff3eec9e4af0db1c6c355
https://github.com/llvm/llvm-project/commit/f8c034140b577c81ddaff3eec9e4af0db1c6c355
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/docs/Tutorials/transform/Ch0.md
Log Message:
-----------
[mlir][docs] Update TD tutorial - Ch0 (#76858)
Updates `generic` as `linalg.generic` (for consistency and to avoid
ambiguity) and a few other fixes.
Commit: 3737712daeef9581e6388fad24f4fb56d89ce032
https://github.com/llvm/llvm-project/commit/3737712daeef9581e6388fad24f4fb56d89ce032
Author: Sergei Lebedev <185856+superbobry at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
Log Message:
-----------
Slightly improved ir.pyi type annotations (#76728)
* Replaced `Any` with static types where appropriate
* Removed undocumented `__str__` and `__repr__` -- these are always
defined via `object`
Commit: dd4dc2111e2a788046b0db81eb274f53591313ff
https://github.com/llvm/llvm-project/commit/dd4dc2111e2a788046b0db81eb274f53591313ff
Author: Chen Zheng <czhengsz at cn.ibm.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
A llvm/test/CodeGen/PowerPC/pr47155-47156.ll
Log Message:
-----------
nfc add cases for pr47156 and pr47155
Commit: 87f1cf04cde146634f060167fb57fedf63b99ce5
https://github.com/llvm/llvm-project/commit/87f1cf04cde146634f060167fb57fedf63b99ce5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
A llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-multiples.ll
Log Message:
-----------
[ConstraintElim] Add tests for int phi with non-one step (NFC)
Commit: 7954c57124b495fbdc73674d71f2e366e4afe522
https://github.com/llvm/llvm-project/commit/7954c57124b495fbdc73674d71f2e366e4afe522
Author: Jannik Silvanus <37809848+jasilvanus at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/IR/GetElementPtrTypeIterator.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/Local.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/IR/Operator.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/test/Transforms/InstCombine/getelementptr.ll
Log Message:
-----------
[IR] Fix GEP offset computations for vector GEPs (#75448)
Vectors are always bit-packed and don't respect the elements' alignment
requirements. This is different from arrays. This means offsets of
vector GEPs need to be computed differently than offsets of array GEPs.
This PR fixes many places that rely on an incorrect pattern
that always relies on `DL.getTypeAllocSize(GTI.getIndexedType())`.
We replace these by usages of `GTI.getSequentialElementStride(DL)`,
which is a new helper function added in this PR.
This changes behavior for GEPs into vectors with element types for which
the (bit) size and alloc size is different. This includes two cases:
* Types with a bit size that is not a multiple of a byte, e.g. i1.
GEPs into such vectors are questionable to begin with, as some elements
are not even addressable.
* Overaligned types, e.g. i16 with 32-bit alignment.
Existing tests are unaffected, but a miscompilation of a new test is fixed.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 2bd6642533ce858c07f1c412e1b8a669c17afb54
https://github.com/llvm/llvm-project/commit/2bd6642533ce858c07f1c412e1b8a669c17afb54
Author: drblallo <blalloscompany at gmail.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/lib/Analysis/DataFlow/DenseAnalysis.cpp
M mlir/test/Analysis/DataFlow/test-next-access.mlir
Log Message:
-----------
[mlir][dataflow]Fix dense backward dataflow intraprocedural hook (#76865)
The dataflow analysis framework within MLIR allows to customize the
transfer function when a `call-like` operation is encuntered.
The check to see if the analysis was executed in intraprocedural mode
was executed after the check to see if the callee had the
CallableOpInterface, and thus intraprocedural analyses would behave as
interpocedural ones when performing indirect calls.
This commit fixes the issue by performing the check for
intraprocedurality first.
Dense forward analyses were already behaving correctly.
https://github.com/llvm/llvm-project/blob/main/mlir/lib/Analysis/DataFlow/DenseAnalysis.cpp#L63
Co-authored-by: massimo <mo.fioravanti at gmail.com>
Commit: 0c23163184e098e1aac128cbbd7b4c2b4bd6bb26
https://github.com/llvm/llvm-project/commit/0c23163184e098e1aac128cbbd7b4c2b4bd6bb26
Author: Mitch Phillips <mitchp at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/IR/LinalgInterfaces.td
M mlir/unittests/Dialect/CMakeLists.txt
R mlir/unittests/Dialect/Linalg/CMakeLists.txt
R mlir/unittests/Dialect/Linalg/LinalgInterfacesTest.cpp
Log Message:
-----------
Revert "[mlir] Add `res()` method to `linalg::ContractionOpInterface` (#76539)"
This reverts commit 53edf12e526704cc251b6a6917319c7cb7a653a0.
Reason: Broke the sanitizer buildbots with a memory leak. More
information available on
https://github.com/llvm/llvm-project/commit/53edf12e526704cc251b6a6917319c7cb7a653a0
Commit: b4ac4d2264123ab2672a9efed99068df8fb750aa
https://github.com/llvm/llvm-project/commit/b4ac4d2264123ab2672a9efed99068df8fb750aa
Author: sstipanovic <146831748+sstipanovic at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
A llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
R llvm/test/CodeGen/AMDGPU/image-atomic-attributes.ll
Log Message:
-----------
[NFC][AMDGPU] Move image-atomic-attributes test to test/Assembler. (#76917)
Commit: 26993f61673e3d9b29785f9baa5bac50c09f8bcf
https://github.com/llvm/llvm-project/commit/26993f61673e3d9b29785f9baa5bac50c09f8bcf
Author: Mitch Phillips <mitchp at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/docs/ClangFormat.rst
M clang/test/Format/clang-format-ignore.cpp
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
Revert "[clang-format] Optimize processing .clang-format-ignore files (#76733)"
This reverts commit 42ec976184acd40436acd7104ad715c60ca3e7ed.
Reason: Broke the sanitizer buildbots. See more information on the
github comment thread at
https://github.com/llvm/llvm-project/commit/42ec976184acd40436acd7104ad715c60ca3e7ed
Commit: 985bb3a20a788b3cda3256084fbdef20296ba8cb
https://github.com/llvm/llvm-project/commit/985bb3a20a788b3cda3256084fbdef20296ba8cb
Author: Alex Zinenko <zinenko at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
Log Message:
-----------
[mlir] fix bytecode writer after c1eab57673ef3eb28
The change in c1eab57 fixed the
behavior of `getDiscardableAttrDictionary` for ops that are not using
properties to only return discardable attributes. Bytecode writer was
relying on the wrong behavior and would assume all attributes are
discardable, without appropriate testing. Fix that and add a test.
Commit: 5ed11e767c0c39a3bc8e035588e7a383849d46a8
https://github.com/llvm/llvm-project/commit/5ed11e767c0c39a3bc8e035588e7a383849d46a8
Author: Alex Zinenko <zinenko at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/lib/Bytecode/Writer/IRNumbering.cpp
Log Message:
-----------
[mlir] don't use magic numbers in IRNumbering.cpp
Bytecode versions have named constants that should be used instead of
magic numbers.
Commit: ce61b0e9a41fb55beaef04610967ccc7b69307f8
https://github.com/llvm/llvm-project/commit/ce61b0e9a41fb55beaef04610967ccc7b69307f8
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/RuntimeLibcalls.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-cmpxchg-outline_atomics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
Log Message:
-----------
Add out-of-line-atomics support to GlobalISel (#74588)
This patch implement the GlobalISel counterpart to
4d7df43ffdb460dddb2877a886f75f45c3fee188.
Commit: ff0c1f20a744b93ab8a9f8b378c5225cf3f4f68f
https://github.com/llvm/llvm-project/commit/ff0c1f20a744b93ab8a9f8b378c5225cf3f4f68f
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[CodeGen] Remove unused variables in TargetLoweringBase.cpp (NFC)
llvm-project/llvm/lib/CodeGen/TargetLoweringBase.cpp:570:12: error: unused variable 'ModeN' [-Werror,-Wunused-variable]
570 | unsigned ModeN, ModelN;
| ^~~~~
llvm-project/llvm/lib/CodeGen/TargetLoweringBase.cpp:570:19: error: unused variable 'ModelN' [-Werror,-Wunused-variable]
570 | unsigned ModeN, ModelN;
| ^~~~~~
2 errors generated.
Commit: 72db578d7149bc9941d45a800fb8be4f79ba24e2
https://github.com/llvm/llvm-project/commit/72db578d7149bc9941d45a800fb8be4f79ba24e2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[DAG] Fix typo in VSELECT SimplifyDemandedVectorElts handling. NFC.
Rename UndefZero -> UndefSel (undefined elements from Sel operand).
Commit: 6bb8d69f2a66da179efec8e0e69fbf55a3296d1c
https://github.com/llvm/llvm-project/commit/6bb8d69f2a66da179efec8e0e69fbf55a3296d1c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] combineLoad - pull out repeated cast<MemSDNode> calls. NFC.
Commit: 43e0723899e909cb2502b34da2003a5774ffb394
https://github.com/llvm/llvm-project/commit/43e0723899e909cb2502b34da2003a5774ffb394
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
Log Message:
-----------
[DAG] BaseIndexOffset::computeAliasing - early out on failed matches. NFCI.
Don't wait to test that all base ptr matches have succeeded
Commit: 5b38ecff6e9d7ef84ba8fd9b1b1e4c9b229dbdb5
https://github.com/llvm/llvm-project/commit/5b38ecff6e9d7ef84ba8fd9b1b1e4c9b229dbdb5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
Log Message:
-----------
[DAG] BaseIndexOffset::equalBaseIndex - early out on failed matches. NFCI.
If we successfully cast only the first base node as GlobalAddressSDNode / ConstantPoolSDNode / FrameIndexSDNode then we can early out as we know that base won't cast as a later type.
Noticed while investigating profiles for potential compile time improvements.
Commit: f45b75949d8ccc9890241ecf9b9ad11349e1d036
https://github.com/llvm/llvm-project/commit/f45b75949d8ccc9890241ecf9b9ad11349e1d036
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[DAG] SimplifyDemandedBits - call demanded elts variant directly for SELECT/SELECT_CC nodes.
Don't rebuild the demanded elts mask every time.
Commit: f5efa74961560070a1e6f127214bcf6b570fef98
https://github.com/llvm/llvm-project/commit/f5efa74961560070a1e6f127214bcf6b570fef98
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
[Sema] When checking for constraint equivalence, do not calculate satisfaction (#74490)
... and only look at equivalence of substituted expressions, not results
of constraint satisfaction.
This is required by the standard when matching redeclarations.
Fixes #74314.
There is already some existing machinery for that in
`TemplateInstantiator` and `Sema` exposed separate functions for
substituting expressions with intention to do that:
- `Sema::SubstExpr` should not evaluate constraints.
- `Sema::SubstConstraintExpr` should.
However, both functions used to be equivalent. Introduce a new function
that does not evaluate constraint and use it when matching declarations.
Also change implementation of `SubstConstraintExpr` to call `SubstExpr`
directly so it's obvious they behave in the same way and add a FIXME to
call out that we might need to revamp this approach in the future.
Commit: 2336f792bc5a1d9195c1bd995b6040c13e73d4e7
https://github.com/llvm/llvm-project/commit/2336f792bc5a1d9195c1bd995b6040c13e73d4e7
Author: kadir çetinkaya <kadircet at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
Log Message:
-----------
[clangd] Dont require confirmation for include-cleaner batch-fixes (#76826)
False negative/positive rate has decreased to the degree that these
extra confirmations no longer provide any value, but only create
friction in the happy case.
When we have false analysis, people usually need to apply the fixes and
run the builds to discover the failure. At that point they can add
relevant IWYU pragmas to guide analysis, and will be more likely to
create bug reports due to extra annoyance :)
Commit: 202a4c0dfb19823a0c0fc737e32d205efaffb7ff
https://github.com/llvm/llvm-project/commit/202a4c0dfb19823a0c0fc737e32d205efaffb7ff
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Fix BUILD after 6ae7f66ff5169ddc5a7b9ab545707042c77e036c
Commit: e147dcbcbc8f92b7f4973eaebe800308f480dd84
https://github.com/llvm/llvm-project/commit/e147dcbcbc8f92b7f4973eaebe800308f480dd84
Author: HaohaiWen <haohai.wen at intel.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
A llvm/test/CodeGen/X86/windows-seh-EHa-RegisterLiveness.ll
Log Message:
-----------
[SEH] Add test to track EHa register liveness verification (#76921)
This test tracks bug of MachineVerifier to check live range segment for
EHa. Async exception can happen at any place within seh scope, not only
the call instruction. Need to teach MachineVerifier to know that.
Commit: ca5d34ec7186f2b5750c7e67dcb8b2d0dc865d8d
https://github.com/llvm/llvm-project/commit/ca5d34ec7186f2b5750c7e67dcb8b2d0dc865d8d
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/docs/Tutorials/transform/Ch1.md
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/test/Dialect/GPU/transform-gpu-failing.mlir
M mlir/test/Dialect/Linalg/tile-to-forall.mlir
M mlir/test/Examples/transform/Ch1/invalidation-1.mlir
Log Message:
-----------
[mlir][TD] Fix the order of return handles (#76929)
Replace (in tests and docs):
%forall, %tiled = transform.structured.tile_using_forall
with (updated order of return handles):
%tiled, %forall = transform.structured.tile_using_forall
Similar change is applied to (in the TD tutorial):
transform.structured.fuse_into_containing_op
This update makes sure that the tests/documentation are consistent with
the Op specifications. Follow-up for #67320 which updated the order of
the return handles for `tile_using_forall`.
Commit: 71b3ead870107e39e998f6480e545eb01d9d28be
https://github.com/llvm/llvm-project/commit/71b3ead870107e39e998f6480e545eb01d9d28be
Author: Martin Storsjö <martin at martin.st>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
Log Message:
-----------
[clang][dataflow] Remove a redundant trailing semicolon. NFC.
This silences the following warning with GCC:
llvm-project/llvm/tools/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp:89:4: warning: extra ‘;’ [-Wpedantic]
89 | };
| ^
| -
Commit: f8122518750e3563a79df22d72c26c3c922f63f2
https://github.com/llvm/llvm-project/commit/f8122518750e3563a79df22d72c26c3c922f63f2
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-multiples.ll
Log Message:
-----------
[ConstraintElim] Use SCEV to check for multiples (#76925)
When adding constraints for induction variables, if the step is not one,
we need to make sure that (end-start) is a multiple of step, otherwise
we might step over the end value.
Currently this only supports one specific pattern for pointers, where
the end is a gep of the start with an appropriate offset.
Generalize this by using SCEV to check for multiples, which also makes
this work for integer IVs.
Commit: 475890cd2e65d0e9fbd37a912cd359f12f1f7668
https://github.com/llvm/llvm-project/commit/475890cd2e65d0e9fbd37a912cd359f12f1f7668
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-insert.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-select.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
Log Message:
-----------
[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)
Instruction cost for CodeSize and Latency/RecipThroughput can be very
different. Considering the diversity of CostKind and vendor-specific
cost, and how they are spread across various TTI functions, it's
becoming quite a challenge to handle. This patch adds an interface
getRISCVInstructionCost to address it.
Commit: 26ff659c39a67fe60517b45d4a954231f77c1350
https://github.com/llvm/llvm-project/commit/26ff659c39a67fe60517b45d4a954231f77c1350
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
Log Message:
-----------
[AMDGPU] Remove some unused check prefixes
Commit: 4de971c230e8202cfd54d4d6c36719db628d35ce
https://github.com/llvm/llvm-project/commit/4de971c230e8202cfd54d4d6c36719db628d35ce
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[clang][ASTImporter] import InstantiatedFromMember of ClassTemplateSpecializationDecl (#76493)
import of `ClassTemplateSpecializationDecl` didn't set
`InstantiatedFromMember` and this makes ast-dump crash. import and set
`InstantiatedFromMember`. fix
[issue](https://github.com/llvm/llvm-project/issues/76469)
Co-authored-by: huqizhi <836744285 at qq.com>
Commit: 62144969bc03490908d46675f3d6645cbe248d25
https://github.com/llvm/llvm-project/commit/62144969bc03490908d46675f3d6645cbe248d25
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
Log Message:
-----------
[ConstraintElim] Add debug output for failed preconditions
Print debug output if a constraint does not get added due to a
failed precondition.
Commit: 9803de0e8e3abbbc94a4265d5847db435897a384
https://github.com/llvm/llvm-project/commit/9803de0e8e3abbbc94a4265d5847db435897a384
Author: Chaitanya <Krishna.Sankisa at amd.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/BinaryFormat/AMDGPUMetadataVerifier.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
Log Message:
-----------
[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)
"hidden_dynamic_lds_size" argument will be added in the reserved section
at offset 120 of the implicit argument layout.
Add "isDynamicLDSUsed" flag to AMDGPUMachineFunction to identify if a
function uses dynamic LDS.
hidden argument will be added in below cases:
- LDS global is used in the kernel.
- Kernel calls a function which uses LDS global.
- LDS pointer is passed as argument to kernel itself.
Commit: 3fd081f71eb6f0cda842995959df86077c2d6559
https://github.com/llvm/llvm-project/commit/3fd081f71eb6f0cda842995959df86077c2d6559
Author: alekuz01 <aleksei.kuzmenko at arm.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/docs/CMake.rst
Log Message:
-----------
[llvm][doc][NFC] Fix typo in documentation in CMake.rst (#76836)
Fix for #71941
Commit: db34a94710bc93970b5a873b1eef5c7ae2a3e046
https://github.com/llvm/llvm-project/commit/db34a94710bc93970b5a873b1eef5c7ae2a3e046
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/test/Transforms/ConstraintElimination/shl.ll
Log Message:
-----------
[ConstraintElim] Add tests for shl nsw decomposition (NFC)
Commit: 4e281e2cb717c9bc6af2c01f56857d352adbe10e
https://github.com/llvm/llvm-project/commit/4e281e2cb717c9bc6af2c01f56857d352adbe10e
Author: Mauro Baladés <mauro.balades at tutanota.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
Log Message:
-----------
[NFC][Clang] Avoid copying Param and Constr (#65488)
Commit: e947b63516c8f9884e84bca000f7e9d9db7701c1
https://github.com/llvm/llvm-project/commit/e947b63516c8f9884e84bca000f7e9d9db7701c1
Author: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
Log Message:
-----------
[AMDGPU][NFC] Update alias test
Alias test should contain alternative names in check lines
Commit: 901a8160a8cb3bda3558fffb8e109485c42affe5
https://github.com/llvm/llvm-project/commit/901a8160a8cb3bda3558fffb8e109485c42affe5
Author: Pol M <polmarcetsarda at gmail.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang/include/clang/AST/DeclCXX.h
M clang/lib/AST/DeclBase.cpp
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[clang] Optimize castToDeclContext for 2% improvement in build times (#76825)
Optimize castToDeclContext for 2% improvement in build times
castToDeclContext is a heavily used function, and as such, it needs to
be kept as slim as feasible to preserve as much performance as possible.
To this end, it was observed that the function was generating suboptimal
assembly code, and putting the most common execution path in the longest
sequence of instructions. This patch addresses this by guiding the
compiler towards generating a lookup table of offsets, which can be used
to perform an addition on the pointer. This results in a 1-2%
improvement on debug builds (and a negligible improvement on release).
To achieve this, the switch was simplified to flatten the if statements
in the default branch. In order to make the values of the switch more
compact, encouraging LLVM to generate a look-up table instead of a jump
table, the AST TableGen generator was modified so it can take order
priority based on class inheritance. This combination allowed for a more
optimal generation of the function. Of note, 2 other functions with an
equivalent structure also needed to be modified.
Fixes #76824
Commit: 96c23ebd3b28f034784eab66393ea9a46e45c6ee
https://github.com/llvm/llvm-project/commit/96c23ebd3b28f034784eab66393ea9a46e45c6ee
Author: Simon Camphausen <simon.camphausen at iml.fraunhofer.de>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitCAttributes.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCTypes.td
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
Log Message:
-----------
[mlir][EmitC] Use declarative assembly format for opaque types and attributes (#76066)
The parser and printer of string attributes were changed to handle
escape sequences. Therefore, we no longer require a custom parser and
printer. Verification is moved from the parser to the verifier
accordingly.
Commit: 79e62315be5b762f399e98c0b638e682eac66322
https://github.com/llvm/llvm-project/commit/79e62315be5b762f399e98c0b638e682eac66322
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
Log Message:
-----------
[SLP]Use revectorized value for extracts from buildvector, beeing
vectorized.
When trying to reuse the extractelement instruction, emitted for the
insertelement instruction, need to check, if the this insertelement
instruction was vectorized. In this case, need to use vectorized value,
not the original insertelement.
Commit: d02471ede56e727d7d16f61bcdecc4f99a2bda02
https://github.com/llvm/llvm-project/commit/d02471ede56e727d7d16f61bcdecc4f99a2bda02
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/fpbits_str.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log10f.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/log2f.cpp
M libc/src/math/generic/logf.cpp
M libc/test/src/stdlib/strtold_test.cpp
M libc/test/src/time/difftime_test.cpp
Log Message:
-----------
[libc][NFC] Simplify `FPBits` (#76835)
This patch reduces the scope of `FPBits` exported variables and
functions.
It also moves storage up into `FPRep` and tries to make the default and
specialized versions of `FPBits` more uniform.
The next step is to move the specialization from `FPBits` to `FPRep` so
we can manipulate floating point representations through `FPType`
alone - that is - independently from the host architecture.
Commit: cd3fb505059b0a6851d75af82f83f65882e6d8e1
https://github.com/llvm/llvm-project/commit/cd3fb505059b0a6851d75af82f83f65882e6d8e1
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/Driver/ToolChains/Arch/Mips.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/stream-error.c
M clang/test/Analysis/stream-non-posix-function.c
M clang/test/Analysis/stream-note.c
M clang/test/Analysis/stream-stdlibraryfunctionargs.c
M clang/test/Analysis/stream.c
M clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M clang/test/Driver/mips-features.c
M clang/test/SemaCXX/template-instantiation.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/fpbits_str.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log10f.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/log2f.cpp
M libc/src/math/generic/logf.cpp
M libc/src/signal/linux/signal_utils.h
M libc/test/src/stdlib/strtold_test.cpp
M libc/test/src/time/difftime_test.cpp
M libcxx/include/__format/format_arg_store.h
M libcxx/test/libcxx/system_reserved_names.gen.py
M lldb/source/Breakpoint/BreakpointResolverAddress.cpp
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.cpp
M lldb/test/API/functionalities/breakpoint/serialize/TestBreakpointSerialization.py
M lldb/unittests/Thread/ThreadTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CMake.rst
M llvm/docs/Extensions.rst
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/RuntimeLibcalls.h
M llvm/include/llvm/IR/GetElementPtrTypeIterator.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/Local.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/AMDGPUMetadataVerifier.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/IR/Operator.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-insert.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-select.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
A llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-cmpxchg-outline_atomics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/MLRegAlloc/dev-mode-extra-features-logging.ll
A llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll
A llvm/test/CodeGen/X86/basic-block-sections-labels-pgo-features.ll
M llvm/test/CodeGen/X86/bfloat.ll
A llvm/test/CodeGen/X86/windows-seh-EHa-RegisterLiveness.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/AMDGPU/literalv216.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt
A llvm/test/MC/Disassembler/X86/apx/adx.txt
M llvm/test/MC/Disassembler/X86/apx/amx-tile.txt
A llvm/test/MC/Disassembler/X86/apx/bmi2.txt
A llvm/test/MC/Disassembler/X86/apx/cet.txt
M llvm/test/MC/Disassembler/X86/apx/cmpccxadd.txt
A llvm/test/MC/Disassembler/X86/apx/dec.txt
A llvm/test/MC/Disassembler/X86/apx/inc.txt
R llvm/test/MC/Disassembler/X86/apx/invept.txt
M llvm/test/MC/Disassembler/X86/apx/invpcid.txt
R llvm/test/MC/Disassembler/X86/apx/invvpid.txt
M llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
M llvm/test/MC/Disassembler/X86/apx/movdiri.txt
R llvm/test/MC/Disassembler/X86/apx/mulx.txt
R llvm/test/MC/Disassembler/X86/apx/rorx.txt
R llvm/test/MC/Disassembler/X86/apx/sarx.txt
A llvm/test/MC/Disassembler/X86/apx/sha.txt
R llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
R llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
R llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
R llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
R llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
R llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
R llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
R llvm/test/MC/Disassembler/X86/apx/shlx.txt
R llvm/test/MC/Disassembler/X86/apx/shrx.txt
A llvm/test/MC/Disassembler/X86/apx/vmx.txt
R llvm/test/MC/Disassembler/X86/apx/wrssd.txt
R llvm/test/MC/Disassembler/X86/apx/wrssq.txt
R llvm/test/MC/Disassembler/X86/apx/wrussd.txt
R llvm/test/MC/Disassembler/X86/apx/wrussq.txt
A llvm/test/MC/X86/apx/adx-att.s
A llvm/test/MC/X86/apx/adx-intel.s
M llvm/test/MC/X86/apx/amx-tile-att.s
M llvm/test/MC/X86/apx/amx-tile-intel.s
A llvm/test/MC/X86/apx/bmi2-att.s
A llvm/test/MC/X86/apx/bmi2-intel.s
A llvm/test/MC/X86/apx/cet-att.s
A llvm/test/MC/X86/apx/cet-intel.s
M llvm/test/MC/X86/apx/cmpccxadd-att.s
M llvm/test/MC/X86/apx/cmpccxadd-intel.s
A llvm/test/MC/X86/apx/dec-att.s
A llvm/test/MC/X86/apx/dec-intel.s
A llvm/test/MC/X86/apx/inc-att.s
A llvm/test/MC/X86/apx/inc-intel.s
R llvm/test/MC/X86/apx/invept-att.s
R llvm/test/MC/X86/apx/invept-intel.s
M llvm/test/MC/X86/apx/invpcid-att.s
M llvm/test/MC/X86/apx/invpcid-intel.s
R llvm/test/MC/X86/apx/invvpid-att.s
R llvm/test/MC/X86/apx/invvpid-intel.s
M llvm/test/MC/X86/apx/movdir64b-att.s
M llvm/test/MC/X86/apx/movdir64b-intel.s
M llvm/test/MC/X86/apx/movdiri-att.s
M llvm/test/MC/X86/apx/movdiri-intel.s
R llvm/test/MC/X86/apx/mulx-att.s
R llvm/test/MC/X86/apx/mulx-intel.s
R llvm/test/MC/X86/apx/pdep-att.s
R llvm/test/MC/X86/apx/pdep-intel.s
R llvm/test/MC/X86/apx/pext-att.s
R llvm/test/MC/X86/apx/pext-intel.s
R llvm/test/MC/X86/apx/rorx-att.s
R llvm/test/MC/X86/apx/rorx-intel.s
R llvm/test/MC/X86/apx/sarx-att.s
R llvm/test/MC/X86/apx/sarx-intel.s
A llvm/test/MC/X86/apx/sha-att.s
A llvm/test/MC/X86/apx/sha-intel.s
R llvm/test/MC/X86/apx/sha1msg1-att.s
R llvm/test/MC/X86/apx/sha1msg1-intel.s
R llvm/test/MC/X86/apx/sha1msg2-att.s
R llvm/test/MC/X86/apx/sha1msg2-intel.s
R llvm/test/MC/X86/apx/sha1nexte-att.s
R llvm/test/MC/X86/apx/sha1nexte-intel.s
R llvm/test/MC/X86/apx/sha1rnds4-att.s
R llvm/test/MC/X86/apx/sha1rnds4-intel.s
R llvm/test/MC/X86/apx/sha256msg1-att.s
R llvm/test/MC/X86/apx/sha256msg1-intel.s
R llvm/test/MC/X86/apx/sha256msg2-att.s
R llvm/test/MC/X86/apx/sha256msg2-intel.s
R llvm/test/MC/X86/apx/sha256rnds2-att.s
R llvm/test/MC/X86/apx/sha256rnds2-intel.s
R llvm/test/MC/X86/apx/shlx-att.s
R llvm/test/MC/X86/apx/shlx-intel.s
R llvm/test/MC/X86/apx/shrx-att.s
R llvm/test/MC/X86/apx/shrx-intel.s
A llvm/test/MC/X86/apx/vmx-att.s
A llvm/test/MC/X86/apx/vmx-intel.s
R llvm/test/MC/X86/apx/wrssd-att.s
R llvm/test/MC/X86/apx/wrssd-intel.s
R llvm/test/MC/X86/apx/wrssq-att.s
R llvm/test/MC/X86/apx/wrssq-intel.s
R llvm/test/MC/X86/apx/wrussd-att.s
R llvm/test/MC/X86/apx/wrussd-intel.s
R llvm/test/MC/X86/apx/wrussq-att.s
R llvm/test/MC/X86/apx/wrussq-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
A llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-multiples.ll
M llvm/test/Transforms/ConstraintElimination/shl.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
A llvm/test/tools/llvm-nm/wasm/linked.yaml
A llvm/test/tools/llvm-objdump/wasm/linked-symbol-table.yaml
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-exegesis/lib/Assembler.h
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
M llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h
M mlir/CMakeLists.txt
M mlir/docs/Tutorials/transform/Ch0.md
M mlir/docs/Tutorials/transform/Ch1.md
M mlir/examples/minimal-opt/README.md
M mlir/include/mlir/Config/mlir-config.h.cmake
M mlir/include/mlir/Conversion/LLVMCommon/TypeConverter.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitCAttributes.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCTypes.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshBase.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.h
A mlir/include/mlir/IR/PDLPatternMatch.h.inc
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Analysis/DataFlow/DenseAnalysis.cpp
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.cpp
M mlir/lib/Conversion/ComplexToLibm/CMakeLists.txt
M mlir/lib/Conversion/MathToLibm/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/TransformOps/CMakeLists.txt
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/IR/CMakeLists.txt
A mlir/lib/IR/PDL/PDLPatternMatch.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Rewrite/ByteCode.h
M mlir/lib/Rewrite/CMakeLists.txt
M mlir/lib/Rewrite/FrozenRewritePatternSet.cpp
M mlir/lib/Rewrite/PatternApplicator.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Analysis/DataFlow/test-next-access.mlir
M mlir/test/CMakeLists.txt
M mlir/test/Dialect/GPU/transform-gpu-failing.mlir
M mlir/test/Dialect/Linalg/tile-to-forall.mlir
M mlir/test/Examples/transform/Ch1/invalidation-1.mlir
M mlir/test/lib/Rewrite/CMakeLists.txt
M mlir/test/lib/Tools/PDLL/CMakeLists.txt
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/tools/mlir-lsp-server/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
M openmp/libomptarget/test/lit.cfg
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 310afe96b91efa0d63ff2a44c6abf26faba91259
https://github.com/llvm/llvm-project/commit/310afe96b91efa0d63ff2a44c6abf26faba91259
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-01-04 (Thu, 04 Jan 2024)
Changed paths:
M clang-tools-extra/clangd/IncludeCleaner.cpp
M clang-tools-extra/clangd/test/include-cleaner-batch-fix.test
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/Template.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/Basic/Targets/AVR.h
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/Driver/ToolChains/Arch/Mips.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/stream-error.c
M clang/test/Analysis/stream-non-posix-function.c
M clang/test/Analysis/stream-note.c
M clang/test/Analysis/stream-stdlibraryfunctionargs.c
M clang/test/Analysis/stream.c
M clang/test/CXX/temp/temp.decls/temp.variadic/p5.cpp
M clang/test/CodeGen/avr/avr-inline-asm-constraints.c
M clang/test/CodeGen/avr/avr-unsupported-inline-asm-constraints.c
M clang/test/Driver/mips-features.c
M clang/test/SemaCXX/template-instantiation.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
M clang/utils/TableGen/ClangASTNodesEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/fpbits_str.h
M libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log10f.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/log2f.cpp
M libc/src/math/generic/logf.cpp
M libc/src/signal/linux/signal_utils.h
M libc/test/src/stdlib/strtold_test.cpp
M libc/test/src/time/difftime_test.cpp
M libcxx/include/__format/format_arg_store.h
M libcxx/test/libcxx/system_reserved_names.gen.py
M lldb/source/Breakpoint/BreakpointResolverAddress.cpp
M lldb/source/Plugins/Process/Windows/Common/TargetThreadWindows.cpp
M lldb/test/API/functionalities/breakpoint/serialize/TestBreakpointSerialization.py
M lldb/unittests/Thread/ThreadTest.cpp
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/CMake.rst
M llvm/docs/Extensions.rst
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/RuntimeLibcalls.h
M llvm/include/llvm/IR/GetElementPtrTypeIterator.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InlineCost.cpp
M llvm/lib/Analysis/Local.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/BinaryFormat/AMDGPUMetadataVerifier.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
M llvm/lib/IR/DataLayout.cpp
M llvm/lib/IR/Operator.cpp
M llvm/lib/IR/Value.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
M llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/PowerPC/PPCFastISel.cpp
M llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
M llvm/lib/Transforms/Scalar/StraightLineStrengthReduce.cpp
M llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-broadcast.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-insert.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-insert_subvector.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-select.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-transpose.ll
M llvm/test/Analysis/CostModel/RISCV/splice.ll
A llvm/test/Assembler/amdgpu-image-atomic-attributes.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-load-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
M llvm/test/CodeGen/AArch64/Atomics/aarch64-cmpxchg-outline_atomics.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic-128.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
A llvm/test/CodeGen/AArch64/fpowi.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/add.v2i16.ll
M llvm/test/CodeGen/AMDGPU/calling-conventions.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/fma.f16.ll
M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
M llvm/test/CodeGen/AMDGPU/fptosi.f16.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-func-hidden-args-v5.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-funcarg-hidden-args-v5.ll
A llvm/test/CodeGen/AMDGPU/hsa-metadata-dynlds-kernarg-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v5.ll
M llvm/test/CodeGen/AMDGPU/immv216.ll
M llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
M llvm/test/CodeGen/AMDGPU/pk_max_f16_literal.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/MLRegAlloc/dev-mode-extra-features-logging.ll
A llvm/test/CodeGen/PowerPC/pr47155-47156.ll
M llvm/test/CodeGen/X86/basic-block-sections-labels-empty-function.ll
A llvm/test/CodeGen/X86/basic-block-sections-labels-pgo-features.ll
M llvm/test/CodeGen/X86/bfloat.ll
A llvm/test/CodeGen/X86/windows-seh-EHa-RegisterLiveness.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage_alias.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/AMDGPU/literalv216.s
M llvm/test/MC/Disassembler/AMDGPU/gfx10_vop3p_literalv216.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3p.txt
A llvm/test/MC/Disassembler/X86/apx/adx.txt
M llvm/test/MC/Disassembler/X86/apx/amx-tile.txt
A llvm/test/MC/Disassembler/X86/apx/bmi2.txt
A llvm/test/MC/Disassembler/X86/apx/cet.txt
M llvm/test/MC/Disassembler/X86/apx/cmpccxadd.txt
A llvm/test/MC/Disassembler/X86/apx/dec.txt
A llvm/test/MC/Disassembler/X86/apx/inc.txt
R llvm/test/MC/Disassembler/X86/apx/invept.txt
M llvm/test/MC/Disassembler/X86/apx/invpcid.txt
R llvm/test/MC/Disassembler/X86/apx/invvpid.txt
M llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
M llvm/test/MC/Disassembler/X86/apx/movdiri.txt
R llvm/test/MC/Disassembler/X86/apx/mulx.txt
R llvm/test/MC/Disassembler/X86/apx/rorx.txt
R llvm/test/MC/Disassembler/X86/apx/sarx.txt
A llvm/test/MC/Disassembler/X86/apx/sha.txt
R llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
R llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
R llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
R llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
R llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
R llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
R llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
R llvm/test/MC/Disassembler/X86/apx/shlx.txt
R llvm/test/MC/Disassembler/X86/apx/shrx.txt
A llvm/test/MC/Disassembler/X86/apx/vmx.txt
R llvm/test/MC/Disassembler/X86/apx/wrssd.txt
R llvm/test/MC/Disassembler/X86/apx/wrssq.txt
R llvm/test/MC/Disassembler/X86/apx/wrussd.txt
R llvm/test/MC/Disassembler/X86/apx/wrussq.txt
A llvm/test/MC/X86/apx/adx-att.s
A llvm/test/MC/X86/apx/adx-intel.s
M llvm/test/MC/X86/apx/amx-tile-att.s
M llvm/test/MC/X86/apx/amx-tile-intel.s
A llvm/test/MC/X86/apx/bmi2-att.s
A llvm/test/MC/X86/apx/bmi2-intel.s
A llvm/test/MC/X86/apx/cet-att.s
A llvm/test/MC/X86/apx/cet-intel.s
M llvm/test/MC/X86/apx/cmpccxadd-att.s
M llvm/test/MC/X86/apx/cmpccxadd-intel.s
A llvm/test/MC/X86/apx/dec-att.s
A llvm/test/MC/X86/apx/dec-intel.s
A llvm/test/MC/X86/apx/inc-att.s
A llvm/test/MC/X86/apx/inc-intel.s
R llvm/test/MC/X86/apx/invept-att.s
R llvm/test/MC/X86/apx/invept-intel.s
M llvm/test/MC/X86/apx/invpcid-att.s
M llvm/test/MC/X86/apx/invpcid-intel.s
R llvm/test/MC/X86/apx/invvpid-att.s
R llvm/test/MC/X86/apx/invvpid-intel.s
M llvm/test/MC/X86/apx/movdir64b-att.s
M llvm/test/MC/X86/apx/movdir64b-intel.s
M llvm/test/MC/X86/apx/movdiri-att.s
M llvm/test/MC/X86/apx/movdiri-intel.s
R llvm/test/MC/X86/apx/mulx-att.s
R llvm/test/MC/X86/apx/mulx-intel.s
R llvm/test/MC/X86/apx/pdep-att.s
R llvm/test/MC/X86/apx/pdep-intel.s
R llvm/test/MC/X86/apx/pext-att.s
R llvm/test/MC/X86/apx/pext-intel.s
R llvm/test/MC/X86/apx/rorx-att.s
R llvm/test/MC/X86/apx/rorx-intel.s
R llvm/test/MC/X86/apx/sarx-att.s
R llvm/test/MC/X86/apx/sarx-intel.s
A llvm/test/MC/X86/apx/sha-att.s
A llvm/test/MC/X86/apx/sha-intel.s
R llvm/test/MC/X86/apx/sha1msg1-att.s
R llvm/test/MC/X86/apx/sha1msg1-intel.s
R llvm/test/MC/X86/apx/sha1msg2-att.s
R llvm/test/MC/X86/apx/sha1msg2-intel.s
R llvm/test/MC/X86/apx/sha1nexte-att.s
R llvm/test/MC/X86/apx/sha1nexte-intel.s
R llvm/test/MC/X86/apx/sha1rnds4-att.s
R llvm/test/MC/X86/apx/sha1rnds4-intel.s
R llvm/test/MC/X86/apx/sha256msg1-att.s
R llvm/test/MC/X86/apx/sha256msg1-intel.s
R llvm/test/MC/X86/apx/sha256msg2-att.s
R llvm/test/MC/X86/apx/sha256msg2-intel.s
R llvm/test/MC/X86/apx/sha256rnds2-att.s
R llvm/test/MC/X86/apx/sha256rnds2-intel.s
R llvm/test/MC/X86/apx/shlx-att.s
R llvm/test/MC/X86/apx/shlx-intel.s
R llvm/test/MC/X86/apx/shrx-att.s
R llvm/test/MC/X86/apx/shrx-intel.s
A llvm/test/MC/X86/apx/vmx-att.s
A llvm/test/MC/X86/apx/vmx-intel.s
R llvm/test/MC/X86/apx/wrssd-att.s
R llvm/test/MC/X86/apx/wrssd-intel.s
R llvm/test/MC/X86/apx/wrssq-att.s
R llvm/test/MC/X86/apx/wrssq-intel.s
R llvm/test/MC/X86/apx/wrussd-att.s
R llvm/test/MC/X86/apx/wrussd-intel.s
R llvm/test/MC/X86/apx/wrussq-att.s
R llvm/test/MC/X86/apx/wrussq-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
A llvm/test/Transforms/ConstraintElimination/monotonic-int-phis-multiples.ll
M llvm/test/Transforms/ConstraintElimination/shl.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/minmax-of-minmax.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/large-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/reg-usage.ll
M llvm/test/Transforms/LoopVectorize/PowerPC/small-loop-rdx.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/SLPVectorizer/X86/gather_extract_from_vectorbuild.ll
A llvm/test/tools/llvm-nm/wasm/linked.yaml
A llvm/test/tools/llvm-objdump/wasm/linked-symbol-table.yaml
M llvm/tools/llvm-exegesis/lib/Assembler.cpp
M llvm/tools/llvm-exegesis/lib/Assembler.h
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
M llvm/unittests/tools/llvm-exegesis/Common/AssemblerUtils.h
M mlir/CMakeLists.txt
M mlir/docs/Tutorials/transform/Ch0.md
M mlir/docs/Tutorials/transform/Ch1.md
M mlir/examples/minimal-opt/README.md
M mlir/include/mlir/Config/mlir-config.h.cmake
M mlir/include/mlir/Conversion/LLVMCommon/TypeConverter.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitCAttributes.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitCTypes.td
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshBase.td
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.td
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.h
A mlir/include/mlir/IR/PDLPatternMatch.h.inc
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Analysis/DataFlow/DenseAnalysis.cpp
M mlir/lib/Bytecode/Writer/BytecodeWriter.cpp
M mlir/lib/Bytecode/Writer/IRNumbering.cpp
M mlir/lib/Conversion/ComplexToLibm/CMakeLists.txt
M mlir/lib/Conversion/MathToLibm/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/TransformOps/CMakeLists.txt
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/IR/CMakeLists.txt
A mlir/lib/IR/PDL/PDLPatternMatch.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Rewrite/ByteCode.h
M mlir/lib/Rewrite/CMakeLists.txt
M mlir/lib/Rewrite/FrozenRewritePatternSet.cpp
M mlir/lib/Rewrite/PatternApplicator.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/Analysis/DataFlow/test-next-access.mlir
M mlir/test/CMakeLists.txt
M mlir/test/Dialect/GPU/transform-gpu-failing.mlir
M mlir/test/Dialect/Linalg/tile-to-forall.mlir
M mlir/test/Examples/transform/Ch1/invalidation-1.mlir
M mlir/test/lib/Rewrite/CMakeLists.txt
M mlir/test/lib/Tools/PDLL/CMakeLists.txt
M mlir/test/lib/Transforms/CMakeLists.txt
M mlir/tools/mlir-lsp-server/CMakeLists.txt
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
M mlir/unittests/Bytecode/BytecodeTest.cpp
M openmp/libomptarget/test/lit.cfg
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/a2afba6c6f3d...310afe96b91e
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