[all-commits] [llvm/llvm-project] ddf009: [NFC][X86] Reorg MC tests for APX promoted instrs ...

[XinWang10 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ddf0096a92e4c2852fd57321f02cbd78e596943c
      https://github.com/llvm/llvm-project/commit/ddf0096a92e4c2852fd57321f02cbd78e596943c
  Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
  Date:   2024-01-04 (Thu, 04 Jan 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrMisc.td
    M llvm/lib/Target/X86/X86InstrShiftRotate.td
    M llvm/test/MC/Disassembler/X86/apx/amx-tile.txt
    A llvm/test/MC/Disassembler/X86/apx/bmi2.txt
    A llvm/test/MC/Disassembler/X86/apx/cet.txt
    M llvm/test/MC/Disassembler/X86/apx/cmpccxadd.txt
    R llvm/test/MC/Disassembler/X86/apx/invept.txt
    M llvm/test/MC/Disassembler/X86/apx/invpcid.txt
    R llvm/test/MC/Disassembler/X86/apx/invvpid.txt
    M llvm/test/MC/Disassembler/X86/apx/movdir64b.txt
    M llvm/test/MC/Disassembler/X86/apx/movdiri.txt
    R llvm/test/MC/Disassembler/X86/apx/mulx.txt
    R llvm/test/MC/Disassembler/X86/apx/rorx.txt
    R llvm/test/MC/Disassembler/X86/apx/sarx.txt
    A llvm/test/MC/Disassembler/X86/apx/sha.txt
    R llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
    R llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
    R llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
    R llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
    R llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
    R llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
    R llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
    R llvm/test/MC/Disassembler/X86/apx/shlx.txt
    R llvm/test/MC/Disassembler/X86/apx/shrx.txt
    A llvm/test/MC/Disassembler/X86/apx/vmx.txt
    R llvm/test/MC/Disassembler/X86/apx/wrssd.txt
    R llvm/test/MC/Disassembler/X86/apx/wrssq.txt
    R llvm/test/MC/Disassembler/X86/apx/wrussd.txt
    R llvm/test/MC/Disassembler/X86/apx/wrussq.txt
    M llvm/test/MC/X86/apx/amx-tile-att.s
    M llvm/test/MC/X86/apx/amx-tile-intel.s
    A llvm/test/MC/X86/apx/bmi2-att.s
    A llvm/test/MC/X86/apx/bmi2-intel.s
    A llvm/test/MC/X86/apx/cet-att.s
    A llvm/test/MC/X86/apx/cet-intel.s
    M llvm/test/MC/X86/apx/cmpccxadd-att.s
    M llvm/test/MC/X86/apx/cmpccxadd-intel.s
    R llvm/test/MC/X86/apx/invept-att.s
    R llvm/test/MC/X86/apx/invept-intel.s
    M llvm/test/MC/X86/apx/invpcid-att.s
    M llvm/test/MC/X86/apx/invpcid-intel.s
    R llvm/test/MC/X86/apx/invvpid-att.s
    R llvm/test/MC/X86/apx/invvpid-intel.s
    M llvm/test/MC/X86/apx/movdir64b-att.s
    M llvm/test/MC/X86/apx/movdir64b-intel.s
    M llvm/test/MC/X86/apx/movdiri-att.s
    M llvm/test/MC/X86/apx/movdiri-intel.s
    R llvm/test/MC/X86/apx/mulx-att.s
    R llvm/test/MC/X86/apx/mulx-intel.s
    R llvm/test/MC/X86/apx/pdep-att.s
    R llvm/test/MC/X86/apx/pdep-intel.s
    R llvm/test/MC/X86/apx/pext-att.s
    R llvm/test/MC/X86/apx/pext-intel.s
    R llvm/test/MC/X86/apx/rorx-att.s
    R llvm/test/MC/X86/apx/rorx-intel.s
    R llvm/test/MC/X86/apx/sarx-att.s
    R llvm/test/MC/X86/apx/sarx-intel.s
    A llvm/test/MC/X86/apx/sha-att.s
    A llvm/test/MC/X86/apx/sha-intel.s
    R llvm/test/MC/X86/apx/sha1msg1-att.s
    R llvm/test/MC/X86/apx/sha1msg1-intel.s
    R llvm/test/MC/X86/apx/sha1msg2-att.s
    R llvm/test/MC/X86/apx/sha1msg2-intel.s
    R llvm/test/MC/X86/apx/sha1nexte-att.s
    R llvm/test/MC/X86/apx/sha1nexte-intel.s
    R llvm/test/MC/X86/apx/sha1rnds4-att.s
    R llvm/test/MC/X86/apx/sha1rnds4-intel.s
    R llvm/test/MC/X86/apx/sha256msg1-att.s
    R llvm/test/MC/X86/apx/sha256msg1-intel.s
    R llvm/test/MC/X86/apx/sha256msg2-att.s
    R llvm/test/MC/X86/apx/sha256msg2-intel.s
    R llvm/test/MC/X86/apx/sha256rnds2-att.s
    R llvm/test/MC/X86/apx/sha256rnds2-intel.s
    R llvm/test/MC/X86/apx/shlx-att.s
    R llvm/test/MC/X86/apx/shlx-intel.s
    R llvm/test/MC/X86/apx/shrx-att.s
    R llvm/test/MC/X86/apx/shrx-intel.s
    A llvm/test/MC/X86/apx/vmx-att.s
    A llvm/test/MC/X86/apx/vmx-intel.s
    R llvm/test/MC/X86/apx/wrssd-att.s
    R llvm/test/MC/X86/apx/wrssd-intel.s
    R llvm/test/MC/X86/apx/wrssq-att.s
    R llvm/test/MC/X86/apx/wrssq-intel.s
    R llvm/test/MC/X86/apx/wrussd-att.s
    R llvm/test/MC/X86/apx/wrussd-intel.s
    R llvm/test/MC/X86/apx/wrussq-att.s
    R llvm/test/MC/X86/apx/wrussq-intel.s

  Log Message:
  -----------
  [NFC][X86] Reorg MC tests for APX promoted instrs (#76697)

As suggested in https://github.com/llvm/llvm-project/pull/76210, this
patch re-organize the mc tests for apx promoted instrs, instr tests
within same cpuid would be listed in one test.
Also add explicit prefix {evex} tests and 8 displacement memory test,
promoted instrs need set No_CD8 to avoid AVX512 compress encoding.