[all-commits] [llvm/llvm-project] 155d58: [AArch64] Avoid jump tables in swiftasync clobber-...

[Ahmed Bougacha via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 155d5849da2b2bfa2da918923d8f148a96c03e72
      https://github.com/llvm/llvm-project/commit/155d5849da2b2bfa2da918923d8f148a96c03e72
  Author: Ahmed Bougacha <ahmed at bougacha.org>
  Date:   2024-01-03 (Wed, 03 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/AArch64/store-swift-async-context-clobber-live-reg.ll

  Log Message:
  -----------
  [AArch64] Avoid jump tables in swiftasync clobber-live-reg test. NFC.

The upstream test relies on jump-tables, which are lowered in
dramatically different ways with later arm64e/ptrauth patches.

Concretely, it's failing for at least two reasons:
- ptrauth removes x16/x17 from tcGPR64 to prevent indirect tail-calls
  from using either register as the callee, conflicting with their usage
  as scratch for the tail-call LR auth checking sequence.  In the
  1/2_available_regs_left tests, this causes the MI scheduler to move
  the load up across some of the inlineasm register clobbers.

- ptrauth adds an x16/x17-using pseudo for jump-table dispatch, which
  looks somewhat different from the regular jump-table dispatch codegen
  by itself, but also prevents compression currently.

They seem like sensible changes.  But they mean the tests aren't really
testing what they're intented to, because there's always an implicit
x16/x17 clobber when using jump-tables.

This updates the test in a way that should work identically regardless
of ptrauth support, with one exception, #1 above, which merely reorders
the load/inlineasm w.r.t. eachother.
I verified the tests still fail the live-reg assertions when
applicable.