[all-commits] [llvm/llvm-project] bdcd7c: [DAGCombiner][RISCV] Preserve disjoint flag in fol...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bdcd7c0ba032873be92bce96e02ebb82a0675616
      https://github.com/llvm/llvm-project/commit/bdcd7c0ba032873be92bce96e02ebb82a0675616
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-03 (Wed, 03 Jan 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/mem.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV] Preserve disjoint flag in folding (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) (#76860)

Since we are shifting both inputs to the original Or by the same amount
and inserting zeros in the LSBs, the result should still be disjoint.