[all-commits] [llvm/llvm-project] 923f6a: [FastISel][AArch64] Compare Instruction Miscompila...

[brendaso1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 923f6ac018e3dd1c86bd4cee05e95680962e1446
      https://github.com/llvm/llvm-project/commit/923f6ac018e3dd1c86bd4cee05e95680962e1446
  Author: brendaso1 <119626341+brendaso1 at users.noreply.github.com>
  Date:   2024-01-03 (Wed, 03 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FastISel.cpp
    M llvm/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll

  Log Message:
  -----------
  [FastISel][AArch64] Compare Instruction Miscompilation Fix (#75993)

When shl is folded in compare instruction, a miscompilation occurs when
the CMP instruction is also sign-extended. For the following IR:

  %op3 = shl i8 %op2, 3
  %tmp3 = icmp eq i8 %tmp2, %op3

It used to generate

   cmp w8, w9, sxtb #3

which means sign extend w9, shift left by 3, and then compare with the
value in w8. However, the original intention of the IR would require
`%op2` to first shift left before extending the operands in the
comparison operation . Moreover, if sign extension is used instead of
zero extension, the sample test would miscompile. This PR creates a fix
for the issue, more specifically to not fold the left shift into the CMP
instruction, and to create a zero-extended value rather than a
sign-extended value.