[all-commits] [llvm/llvm-project] 9e1ad3: [RISCV] Remove blank lines at the end of testcases...

[Jim Lin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9e1ad3cff6a855fdfdc1d91323e2021726da04ea
      https://github.com/llvm/llvm-project/commit/9e1ad3cff6a855fdfdc1d91323e2021726da04ea
  Author: Jim Lin <jim at andestech.com>
  Date:   2024-01-02 (Tue, 02 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/bittest.ll
    M llvm/test/CodeGen/RISCV/compress-inline-asm.ll
    M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
    M llvm/test/CodeGen/RISCV/div_minsize.ll
    M llvm/test/CodeGen/RISCV/double-select-icmp.ll
    M llvm/test/CodeGen/RISCV/float-imm.ll
    M llvm/test/CodeGen/RISCV/float-select-verify.ll
    M llvm/test/CodeGen/RISCV/fmax-fmin.ll
    M llvm/test/CodeGen/RISCV/half-select-icmp.ll
    M llvm/test/CodeGen/RISCV/init-array.ll
    M llvm/test/CodeGen/RISCV/neg-abs.ll
    M llvm/test/CodeGen/RISCV/pr63816.ll
    M llvm/test/CodeGen/RISCV/reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadba.ll
    M llvm/test/CodeGen/RISCV/rv32xtheadbs.ll
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
    M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
    M llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadba.ll
    M llvm/test/CodeGen/RISCV/rv64xtheadbs.ll
    M llvm/test/CodeGen/RISCV/rvv/binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll
    M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesdf.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesdm.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesef.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesem.ll
    M llvm/test/CodeGen/RISCV/rvv/vaesz.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
    M llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsm4r.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll
    M llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll
    M llvm/test/CodeGen/RISCV/saverestore-scs.ll
    M llvm/test/CodeGen/RISCV/split-urem-by-constant.ll
    M llvm/test/CodeGen/RISCV/switch-width.ll
    M llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll
    M llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll
    M llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll

  Log Message:
  -----------
  [RISCV] Remove blank lines at the end of testcases. NFC.