[all-commits] [llvm/llvm-project] f18536: [VPlan] Model address separately. (#72164)

[Florian Hahn via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f18536d6421eb43779e43260a35ac39109a8a021
      https://github.com/llvm/llvm-project/commit/f18536d6421eb43779e43260a35ac39109a8a021
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2024-01-01 (Mon, 01 Jan 2024)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/lib/Transforms/Vectorize/VPlan.h
    M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
    M llvm/lib/Transforms/Vectorize/VPlanValue.h
    M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/epilog-vectorization-widen-inductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-load-store.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleaving-reduction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-inloop-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect-strict-reductions.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-fneg.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-multiexit.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-runtime-check-size-based-threshold.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-forced.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-unroll.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll
    M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
    M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
    M llvm/test/Transforms/LoopVectorize/PowerPC/optimal-epilog-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
    M llvm/test/Transforms/LoopVectorize/RISCV/uniform-load-store.ll
    M llvm/test/Transforms/LoopVectorize/X86/conversion-cost.ll
    M llvm/test/Transforms/LoopVectorize/X86/epilog-vectorization-inductions.ll
    M llvm/test/Transforms/LoopVectorize/X86/fixed-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
    M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
    M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
    M llvm/test/Transforms/LoopVectorize/X86/masked_load_store.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
    M llvm/test/Transforms/LoopVectorize/X86/reduction-fastmath.ll
    M llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll
    M llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
    M llvm/test/Transforms/LoopVectorize/float-induction.ll
    M llvm/test/Transforms/LoopVectorize/induction.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
    M llvm/test/Transforms/LoopVectorize/reduction-odd-interleave-counts.ll
    M llvm/test/Transforms/LoopVectorize/scalable-inductions.ll
    M llvm/test/Transforms/LoopVectorize/scalable-loop-unpredicated-body-scalar-tail.ll
    M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
    M llvm/test/Transforms/LoopVectorize/vplan-dot-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-iv-transforms.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
    M llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
    M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
    M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
    M llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
    M llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
    M llvm/test/Transforms/PhaseOrdering/X86/vector-reduction-known-first-value.ll

  Log Message:
  -----------
  [VPlan] Model address separately. (#72164)

Move vector pointer generation to a separate VPVectorPointerRecipe.
This untangles address computation from the memory recipes future
and is also needed to enable explicit unrolling in VPlan.

https://github.com/llvm/llvm-project/pull/72164