[all-commits] [llvm/llvm-project] 1c87d5: [AArch64][GlobalISel] Lower fminnm/fmaxnm through ...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1c87d5c4fc55cdd67bc879d918480148e64016be
      https://github.com/llvm/llvm-project/commit/1c87d5c4fc55cdd67bc879d918480148e64016be
  Author: David Green <david.green at arm.com>
  Date:   2023-12-28 (Thu, 28 Dec 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/arm64-vmax.ll
    M llvm/test/CodeGen/AArch64/arm64-vminmaxnm.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Lower fminnm/fmaxnm through Global ISel

Whilst this might technically not be correct if a combine treats signed zeroes
differently, where the neon operations are more defined than the minnum/maxnum
nodes. It mirrors what SDAG does, which allows us to lower aarch64_neon_fminnm
and aarch64_neon_fmaxnm through the existing selection patterns.