[all-commits] [llvm/llvm-project] fdb876: [LSR][TTI][RISCV] Disable terminator folding for R...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fdb87640ee2be63af9b0e0cd943cb13d79686a03
      https://github.com/llvm/llvm-project/commit/fdb87640ee2be63af9b0e0cd943cb13d79686a03
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-27 (Wed, 27 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/CodeGen/RISCV/branch-on-zero.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/Transforms/LoopStrengthReduce/RISCV/lsr-cost-compare.ll

  Log Message:
  -----------
  [LSR][TTI][RISCV] Disable terminator folding for RISC-V.

This is a partial revert of e947f953370abe8ffc8713b8f3250a3ec39599fe.

It caused a miscompile in downstream testing.

Spoke with Philip offline. We believe the issue is that LSR needs to
make sure the Step of the other AddRec is non-zero. Reverting until
Philip is back from vacation.