[all-commits] [llvm/llvm-project] 6f8507: [M68k] U/SMULd32d16 are not supposed to be communi...

Min-Yih Hsu via All-commits all-commits at lists.llvm.org
Tue Dec 26 20:59:13 PST 2023


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f85075ff7281be1802c9fd30758d34b67481a1e
      https://github.com/llvm/llvm-project/commit/6f85075ff7281be1802c9fd30758d34b67481a1e
  Author: Min-Yih Hsu <min at myhsu.dev>
  Date:   2023-12-26 (Tue, 26 Dec 2023)

  Changed paths:
    M llvm/lib/Target/M68k/M68kInstrArithmetic.td
    M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
    M llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll

  Log Message:
  -----------
  [M68k] U/SMULd32d16 are not supposed to be communitive

M68k only has 16-bit x 16-bit -> 32-bit variant for multiplications
taking 16-bit operands. We still define two input operands for this
class of instructions, and tie the first operand to the result value.
The problem is that the two operands have different register classes
(DR32 and DR16) hence making these instructions communitive produces
invalid MachineInstr (though the final assembly will still be correct).


  Commit: 2476e2a91140b57ca3ad0792597be4f4d20ddb1a
      https://github.com/llvm/llvm-project/commit/2476e2a91140b57ca3ad0792597be4f4d20ddb1a
  Author: Min-Yih Hsu <min at myhsu.dev>
  Date:   2023-12-26 (Tue, 26 Dec 2023)

  Changed paths:
    M llvm/lib/Target/M68k/M68kISelLowering.cpp
    M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
    M llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll

  Log Message:
  -----------
  [M68k] Optimize for overflow arithmetics that will never overflow

We lower overflow arithmetics to its M68kISD counterparts that produce
results of {i16/i32, i8} in which the second resut represents CCR. In
the event where we're certain there won't be an overflow, for instance
8 & 16-bit multiplications, we simply use zero in replacement of the
second result.
This patch replaces M68kISD::CMOV that takes this kind of zero or
all-ones CCR as condition value with its corresponding operand value.


Compare: https://github.com/llvm/llvm-project/compare/23b82c987d69...2476e2a91140


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