[all-commits] [llvm/llvm-project] af837d: [RISCV][DAG] Teach computeKnownBits consider SEW/L...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: af837d44c7e126eca16426531ed54d94083f3359
      https://github.com/llvm/llvm-project/commit/af837d44c7e126eca16426531ed54d94083f3359
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2023-12-25 (Mon, 25 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvl-ext.ll
    A llvm/test/CodeGen/RISCV/rvv/vsetvlmax-ext.ll

  Log Message:
  -----------
  [RISCV][DAG] Teach computeKnownBits consider SEW/LMUL/AVL for vsetvli. (#76158)

This patch also add tests whose masks are too narrow to combine. I think
it can help us to find out bugs caused by too large known bits.