[all-commits] [llvm/llvm-project] 4b6968: [AArch64] Implement spill/fill of predicate pair r...

[Momchil Velikov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4b6968952e653cb4da301d404717899393e4c530
      https://github.com/llvm/llvm-project/commit/4b6968952e653cb4da301d404717899393e4c530
  Author: Momchil Velikov <momchil.velikov at arm.com>
  Date:   2023-12-22 (Fri, 22 Dec 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir
    A llvm/test/CodeGen/AArch64/sve-pred-pair-spill-fill.ll

  Log Message:
  -----------
  [AArch64] Implement spill/fill of predicate pair register classes (#76068)

We are getting ICE with, e.g.
```
#include <arm_sve.h>

 void g();
 svboolx2_t f0(int64_t i, int64_t n) {
     svboolx2_t r = svwhilelt_b16_x2(i, n);
     g();
     return r;
 }
```