[all-commits] [llvm/llvm-project] 033ec0: [Clang][Sema] Fix Wswitch-default bad warning in t...
Vitaly Buka via All-commits
all-commits at lists.llvm.org
Thu Dec 21 22:27:51 PST 2023
Branch: refs/heads/users/vitalybuka/spr/hwasan-make-stack-variables-output-consistent-with-globals
Home: https://github.com/llvm/llvm-project
Commit: 033ec098be730bff04bfb929d254ce57e5ec8534
https://github.com/llvm/llvm-project/commit/033ec098be730bff04bfb929d254ce57e5ec8534
Author: hstk30-hw <hanwei62 at huawei.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M clang/lib/Sema/SemaStmt.cpp
R clang/test/Sema/switch-default.c
A clang/test/Sema/switch-default.cpp
Log Message:
-----------
[Clang][Sema] Fix Wswitch-default bad warning in template (#76007)
https://github.com/llvm/llvm-project/pull/73077 added -Wswitch-default
diagnostic but it produced false positives in templates. This PR will
address that. https://github.com/llvm/llvm-project/issues/75943
Commit: 7db28dd3f897a8a851bb52741e2de6959a46ddf0
https://github.com/llvm/llvm-project/commit/7db28dd3f897a8a851bb52741e2de6959a46ddf0
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M compiler-rt/lib/hwasan/hwasan_report.cpp
A compiler-rt/test/hwasan/TestCases/stack-overflow.c
M compiler-rt/test/hwasan/TestCases/stack-uar-dynamic.c
M compiler-rt/test/hwasan/TestCases/stack-uar.c
A compiler-rt/test/hwasan/TestCases/stack-underflow.c
Log Message:
-----------
[hwasan] Classify stack overflow, and use after scope (#76133)
We can't distinguish UAR and UAS, but by definition
UAR is already UAS.
Commit: c99670ba513529b3ab6a649be7377b863dc110be
https://github.com/llvm/llvm-project/commit/c99670ba513529b3ab6a649be7377b863dc110be
Author: Matthias Springer <me at m-sp.org>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Vector/ops.mlir
Log Message:
-----------
[mlir][vector] `LoadOp`/`StoreOp`: Allow 0-D vectors (#76134)
Similar to `vector.transfer_read`/`vector.transfer_write`, allow 0-D
vectors.
This commit fixes
`mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir`
when verifying the IR after each pattern (#74270). That test produces a
temporary 0-D load/store op.
Commit: c03745d23a22fea669ccc3e481f52ddf3d3f0406
https://github.com/llvm/llvm-project/commit/c03745d23a22fea669ccc3e481f52ddf3d3f0406
Author: eric <eric at efcs.ca>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
Log Message:
-----------
libc++-infa: Hotfix runner group
The runners-32 group is broken, for reasons...
The easiest fix is to move the jobs to runners-8.
(which needs to be renamed, because they're all actually 30 core
machines)
Commit: 62d8ae0a1e7b80a91dc579dc22b335bb22ed07f8
https://github.com/llvm/llvm-project/commit/62d8ae0a1e7b80a91dc579dc22b335bb22ed07f8
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86InstrTBM.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InstrXOP.td
Log Message:
-----------
[X86][NFC] Remove class (VEX/EVEX/XOP)_4V and add class VVVV
`VEX_4V` does not look simpler than `VEX, VVVV`. It's kind of confusing
b/c classes like `VEX_L`, `VEX_LIG` do not imply `VEX` but it does.
For APX, we have promote EVEX, NDD, NF and NDD_NF instructions. All of
the 4 variants are in EVEX space and NDD/NDD_NF set the VVVV fields.
To extract the common fields (e.g EVEX) into a class and set VVVV
conditionally, we need VVVV to not imply other prefixes.
Commit: 847a6f8f0a6b9b98f2a219c7af59306e9b03b796
https://github.com/llvm/llvm-project/commit/847a6f8f0a6b9b98f2a219c7af59306e9b03b796
Author: Ryan Holt <ryanholt at mathworks.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/test/Integration/Dialect/Memref/cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/load-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/reinterpret-cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/subview-runtime-verification.mlir
Log Message:
-----------
[mlir][MemRef] Add runtime bounds checking (#75817)
This change adds (runtime) bounds checks for `memref` ops using the
existing `RuntimeVerifiableOpInterface`. For `memref.load` and
`memref.store`, we check that the indices are in-bounds of the memref's
index space. For `memref.reinterpret_cast` and `memref.subview` we check
that the resulting address space is in-bounds of the input memref's
address space.
Commit: 26ddf4eee2a009147faa3000c55d7822c2087dce
https://github.com/llvm/llvm-project/commit/26ddf4eee2a009147faa3000c55d7822c2087dce
Author: Fangrui Song <i at maskray.me>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M lld/ELF/InputSection.cpp
M lld/test/ELF/debug-dead-reloc-32.s
M lld/test/ELF/debug-dead-reloc.s
Log Message:
-----------
[ELF] Change .debug_names tombstone value to UINT32_MAX/UINT64_MAX (#74686)
`clang -g -gpubnames -fdebug-types-section` now emits .debug_names
section with references to local type unit entries defined in COMDAT
.debug_info sections.
```
.section .debug_info,"G", at progbits,5657452045627120676,comdat
.Ltu_begin0:
...
.section .debug_names,"", at progbits
...
// DWARF32
.long .Ltu_begin0 # Type unit 0
// DWARF64
// .long .Ltu_begin0 # Type unit 0
```
When `.Ltu_begin0` is relative to a non-prevailing .debug_info section,
the relocation resolves to 0, which is a valid offset within the
.debug_info section.
```
cat > a.cc <<e
struct A { int x; };
inline A foo() { return {1}; }
int main() { foo(); }
e
cat > b.cc <<e
struct A { int x; };
inline A foo() { return {1}; }
void use() { foo(); }
e
clang++ -g -gpubnames -fdebug-types-section -fuse-ld=lld a.cc b.cc -o old
```
```
% llvm-dwarfdump old
...
Local Type Unit offsets [
LocalTU[0]: 0x00000000
]
...
Local Type Unit offsets [
LocalTU[0]: 0x00000000 // indistinguishable from a valid offset within .debug_info
]
```
https://dwarfstd.org/issues/231013.1.html proposes that we use a
tombstone value instead to inform consumers. This patch implements the
idea. The second LocalTU entry will now use 0xffffffff.
https://reviews.llvm.org/D84825 has a TODO that we should switch the
tombstone value for most `.debug_*` sections to UINT64_MAX. We have
postponed the change for more than three years for consumers to migrate.
At some point we shall make the change, so that .debug_names is no long
different from other debug section that is not .debug_loc/.debug_ranges.
Co-authored-by: Alexander Yermolovich <ayermolo at meta.com>
Commit: a03c53c53082ae14d5af44a0cf7fa4626ab3f6f3
https://github.com/llvm/llvm-project/commit/a03c53c53082ae14d5af44a0cf7fa4626ab3f6f3
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
A mlir/test/Target/SPIRV/physical-storage-buffer.mlir
Log Message:
-----------
[mlir][spirv] Add physical storage buffer extension test. NFC. (#76196)
This test demonstrates how the PhysicalStorageBuffer extension can be
used end-2-end in a spir-v module.
This module has been verified to pass serialization, deserialization,
and validation with spirv-val.
Commit: 248fba0cd806a0f6bf4b0f12979f2185f2bed111
https://github.com/llvm/llvm-project/commit/248fba0cd806a0f6bf4b0f12979f2185f2bed111
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
AMDGPU: Remove pointless setOperationAction for xint_to_fp
The legalize action for uint_to_fp/sint_to_fp uses the source integer
type, not the result FP type so setting an action on an FP type does
nothing.
Commit: 0ccc1e7acdda4488a5ae680a4cead6cdd238efab
https://github.com/llvm/llvm-project/commit/0ccc1e7acdda4488a5ae680a4cead6cdd238efab
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/test/CodeGen/AArch64/arm64-addrmode.ll
Log Message:
-----------
Revert "[AArch64] Fold more load.x into load.i with large offset"
Issue #76202
This reverts commit f5687636415969e6d945659a0b78734abdfb0f06.
Commit: beffa1e1f689f1d57079e9721df23ea89f1b730c
https://github.com/llvm/llvm-project/commit/beffa1e1f689f1d57079e9721df23ea89f1b730c
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M compiler-rt/test/hwasan/TestCases/strip_path_prefix.c
Log Message:
-----------
[test][hwasan] Try to fix Android bot
https://lab.llvm.org/buildbot/#/builders/77/builds/33152/steps/21/logs/stdio
Commit: 50ed3b1eccd8497e3546f1f3cd6bd7631c6dc20e
https://github.com/llvm/llvm-project/commit/50ed3b1eccd8497e3546f1f3cd6bd7631c6dc20e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M llvm/test/CodeGen/AMDGPU/bf16.ll
Log Message:
-----------
AMDGPU: Workaround a divergent return value bug in test
Commit: c7952d886060bf2fed7d3a4c08d5636db642a3c1
https://github.com/llvm/llvm-project/commit/c7952d886060bf2fed7d3a4c08d5636db642a3c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Log Message:
-----------
AMDGPU: Add a few more bfloat codegen tests
Commit: cca63f9a363e1ce1b61ed6d4fb33b66d603eb388
https://github.com/llvm/llvm-project/commit/cca63f9a363e1ce1b61ed6d4fb33b66d603eb388
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
R llvm/docs/llvm-objdump.1
Log Message:
-----------
[Docs] Remove llvm-objdump man page (#75759)
This patch removes the explicit llvm-objdump man page. By enabling
sphinx man page output with `-DLLVM_ENABLE_SPHINX=ON` and
`-DSPHINX_OUTPUT_MAN=ON`, we can generate man pages for all the llvm
binary utilities from the restructured text documentation. Having an
additional man page upstream increases fragementation and maintenance.
Commit: bb7f8f7938bf486ce67e824c94e9c87767694710
https://github.com/llvm/llvm-project/commit/bb7f8f7938bf486ce67e824c94e9c87767694710
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M compiler-rt/test/hwasan/TestCases/stack-uas.c
Log Message:
-----------
[test][hwasan] Update another test after #76133
Commit: 782cf12d1145cccfa786f244e46561c424b95982
https://github.com/llvm/llvm-project/commit/782cf12d1145cccfa786f244e46561c424b95982
Author: Artur Pilipenko <apilipenko at azul.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M llvm/utils/chunk-print-before-all.py
Log Message:
-----------
Fix chunk-print-before-all script
After c718336c the output of print-before/print-after was changed.
A semicolon was added before the banner "*** IR Dump ..." and this
change broke chunk-print-before-all script.
This change makes it more resilient to small output format variations.
Commit: 4d1cd38c95d317f1b6b331ea811f7de8592b4ed6
https://github.com/llvm/llvm-project/commit/4d1cd38c95d317f1b6b331ea811f7de8592b4ed6
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Log Message:
-----------
DAG: Handle promotion of fcanonicalize
This avoids a regression in a future commit
Commit: 7b3323fffb2609b243d53c650d28c8760a144898
https://github.com/llvm/llvm-project/commit/7b3323fffb2609b243d53c650d28c8760a144898
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2023-12-22 (Fri, 22 Dec 2023)
Changed paths:
M llvm/lib/Target/X86/X86InstrSystem.td
A llvm/test/MC/Disassembler/X86/apx/wrssd.txt
A llvm/test/MC/Disassembler/X86/apx/wrssq.txt
A llvm/test/MC/Disassembler/X86/apx/wrussd.txt
A llvm/test/MC/Disassembler/X86/apx/wrussq.txt
A llvm/test/MC/X86/apx/wrssd-att.s
A llvm/test/MC/X86/apx/wrssd-intel.s
A llvm/test/MC/X86/apx/wrssq-att.s
A llvm/test/MC/X86/apx/wrssq-intel.s
A llvm/test/MC/X86/apx/wrussd-att.s
A llvm/test/MC/X86/apx/wrussd-intel.s
A llvm/test/MC/X86/apx/wrussq-att.s
A llvm/test/MC/X86/apx/wrussq-intel.s
Log Message:
-----------
[X86][MC] Support Enc/Dec for EGPR for promoted CET instruction (#76023)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted CET instruction
in EVEX space.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Commit: f25bcfbb291e3d213eaded5cfa84d3d4e7002052
https://github.com/llvm/llvm-project/commit/f25bcfbb291e3d213eaded5cfa84d3d4e7002052
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M compiler-rt/test/hwasan/TestCases/strip_path_prefix.c
Log Message:
-----------
[test][hwasan] XFAIL new test which fails for unknown reason
Commit: fb23e77533bc871212ad624908649a1544f8dc4e
https://github.com/llvm/llvm-project/commit/fb23e77533bc871212ad624908649a1544f8dc4e
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M clang/lib/Sema/SemaStmt.cpp
R clang/test/Sema/switch-default.c
A clang/test/Sema/switch-default.cpp
M compiler-rt/lib/hwasan/hwasan_report.cpp
M compiler-rt/test/hwasan/TestCases/stack-uas.c
M compiler-rt/test/hwasan/TestCases/strip_path_prefix.c
M lld/ELF/InputSection.cpp
M lld/test/ELF/debug-dead-reloc-32.s
M lld/test/ELF/debug-dead-reloc.s
R llvm/docs/llvm-objdump.1
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrTBM.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InstrXOP.td
M llvm/test/CodeGen/AArch64/arm64-addrmode.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
A llvm/test/MC/Disassembler/X86/apx/wrssd.txt
A llvm/test/MC/Disassembler/X86/apx/wrssq.txt
A llvm/test/MC/Disassembler/X86/apx/wrussd.txt
A llvm/test/MC/Disassembler/X86/apx/wrussq.txt
A llvm/test/MC/X86/apx/wrssd-att.s
A llvm/test/MC/X86/apx/wrssd-intel.s
A llvm/test/MC/X86/apx/wrssq-att.s
A llvm/test/MC/X86/apx/wrssq-intel.s
A llvm/test/MC/X86/apx/wrussd-att.s
A llvm/test/MC/X86/apx/wrussd-intel.s
A llvm/test/MC/X86/apx/wrussq-att.s
A llvm/test/MC/X86/apx/wrussq-intel.s
M llvm/utils/chunk-print-before-all.py
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Integration/Dialect/Memref/cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/load-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/reinterpret-cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/subview-runtime-verification.mlir
A mlir/test/Target/SPIRV/physical-storage-buffer.mlir
Log Message:
-----------
[𝘀𝗽𝗿] changes introduced through rebase
Created using spr 1.3.4
[skip ci]
Commit: 61794d231e130823b9f5929a8a2ecbaa269a39a9
https://github.com/llvm/llvm-project/commit/61794d231e130823b9f5929a8a2ecbaa269a39a9
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2023-12-21 (Thu, 21 Dec 2023)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M clang/lib/Sema/SemaStmt.cpp
R clang/test/Sema/switch-default.c
A clang/test/Sema/switch-default.cpp
M compiler-rt/lib/hwasan/hwasan_report.cpp
M compiler-rt/test/hwasan/TestCases/stack-uas.c
M compiler-rt/test/hwasan/TestCases/strip_path_prefix.c
M lld/ELF/InputSection.cpp
M lld/test/ELF/debug-dead-reloc-32.s
M lld/test/ELF/debug-dead-reloc.s
R llvm/docs/llvm-objdump.1
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/X86/X86InstrAMX.td
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86InstrSystem.td
M llvm/lib/Target/X86/X86InstrTBM.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86InstrXOP.td
M llvm/test/CodeGen/AArch64/arm64-addrmode.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/function-args.ll
M llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
A llvm/test/MC/Disassembler/X86/apx/wrssd.txt
A llvm/test/MC/Disassembler/X86/apx/wrssq.txt
A llvm/test/MC/Disassembler/X86/apx/wrussd.txt
A llvm/test/MC/Disassembler/X86/apx/wrussq.txt
A llvm/test/MC/X86/apx/wrssd-att.s
A llvm/test/MC/X86/apx/wrssd-intel.s
A llvm/test/MC/X86/apx/wrssq-att.s
A llvm/test/MC/X86/apx/wrssq-intel.s
A llvm/test/MC/X86/apx/wrussd-att.s
A llvm/test/MC/X86/apx/wrussd-intel.s
A llvm/test/MC/X86/apx/wrussq-att.s
A llvm/test/MC/X86/apx/wrussq-intel.s
M llvm/utils/chunk-print-before-all.py
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/lib/Dialect/MemRef/Transforms/RuntimeOpVerification.cpp
M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
M mlir/test/Dialect/Vector/ops.mlir
M mlir/test/Integration/Dialect/Memref/cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/load-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/reinterpret-cast-runtime-verification.mlir
A mlir/test/Integration/Dialect/Memref/subview-runtime-verification.mlir
A mlir/test/Target/SPIRV/physical-storage-buffer.mlir
Log Message:
-----------
rebase
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/5db9ccd1d5b1...61794d231e13
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