[all-commits] [llvm/llvm-project] c99670: [mlir][vector] `LoadOp`/`StoreOp`: Allow 0-D vecto...

[Matthias Springer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c99670ba513529b3ab6a649be7377b863dc110be
      https://github.com/llvm/llvm-project/commit/c99670ba513529b3ab6a649be7377b863dc110be
  Author: Matthias Springer <me at m-sp.org>
  Date:   2023-12-22 (Fri, 22 Dec 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir][vector] `LoadOp`/`StoreOp`: Allow 0-D vectors (#76134)

Similar to `vector.transfer_read`/`vector.transfer_write`, allow 0-D
vectors.

This commit fixes
`mlir/test/Dialect/Vector/vector-transfer-to-vector-load-store.mlir`
when verifying the IR after each pattern (#74270). That test produces a
temporary 0-D load/store op.