[all-commits] [llvm/llvm-project] e64f5d: [RISCV] Replace RISCVISD::VP_MERGE_VL with a new n...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e64f5d6305c447b1ec3bc31128753b28f4e87f32
      https://github.com/llvm/llvm-project/commit/e64f5d6305c447b1ec3bc31128753b28f4e87f32
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-21 (Thu, 21 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Replace RISCVISD::VP_MERGE_VL with a new node that has a separate passthru operand. (#75682)

ISD::VP_MERGE treats the false operand as the source for elements past
VL. The vmerge instruction encodes 3 registers and treats the vd
register as the source for the tail.

This patch adds a new ISD opcode that models the tail source explicitly.
During lowering we copy the false operand to this operand.

I think we can merge RISCVISD::VSELECT_VL with this new opcode by using
an UNDEF passthru, but I'll save that for another patch.