[all-commits] [llvm/llvm-project] b03f0c: [RISCV] Add sifive-p450 CPU. (#75760)

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b03f0c596a180399f7730ed75d78055c81b3d771
      https://github.com/llvm/llvm-project/commit/b03f0c596a180399f7730ed75d78055c81b3d771
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-20 (Wed, 20 Dec 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add sifive-p450 CPU. (#75760)

This is an out of order core with no vector unit. More information:
https://www.sifive.com/cores/performance-p450-470

Scheduler model and other tuning will come in separate patches.