[all-commits] [llvm/llvm-project] f3dcc0: [LLVM][AArch64][tblgen]: Match clamp pattern (#75529)

[Hassnaa Hamdi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3dcc0cba982f1e7d6089c5faa2a7c7c7a743e65
      https://github.com/llvm/llvm-project/commit/f3dcc0cba982f1e7d6089c5faa2a7c7c7a743e65
  Author: Hassnaa Hamdi <hassnaa.hamdi at arm.com>
  Date:   2023-12-20 (Wed, 20 Dec 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll

  Log Message:
  -----------
  [LLVM][AArch64][tblgen]: Match clamp pattern (#75529)

Add isel pattern to replase min(max(v1,v2),v3) by clamp
Add tests for uclamp, sclamp, bfclamp, fclamp.