[all-commits] [llvm/llvm-project] 037c22: [X86][MC] Support Enc/Dec for EGPR for promoted SH...
XinWang10 via All-commits
all-commits at lists.llvm.org
Tue Dec 19 21:55:04 PST 2023
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 037c220702802ea8f26c359c30b69a1c8d33ef0d
https://github.com/llvm/llvm-project/commit/037c220702802ea8f26c359c30b69a1c8d33ef0d
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2023-12-20 (Wed, 20 Dec 2023)
Changed paths:
M llvm/lib/Target/X86/X86InstrAsmAlias.td
M llvm/lib/Target/X86/X86InstrSSE.td
A llvm/test/MC/Disassembler/X86/apx/sha1msg1.txt
A llvm/test/MC/Disassembler/X86/apx/sha1msg2.txt
A llvm/test/MC/Disassembler/X86/apx/sha1nexte.txt
A llvm/test/MC/Disassembler/X86/apx/sha1rnds4.txt
A llvm/test/MC/Disassembler/X86/apx/sha256msg1.txt
A llvm/test/MC/Disassembler/X86/apx/sha256msg2.txt
A llvm/test/MC/Disassembler/X86/apx/sha256rnds2.txt
A llvm/test/MC/X86/apx/sha1msg1-att.s
A llvm/test/MC/X86/apx/sha1msg1-intel.s
A llvm/test/MC/X86/apx/sha1msg2-att.s
A llvm/test/MC/X86/apx/sha1msg2-intel.s
A llvm/test/MC/X86/apx/sha1nexte-att.s
A llvm/test/MC/X86/apx/sha1nexte-intel.s
A llvm/test/MC/X86/apx/sha1rnds4-att.s
A llvm/test/MC/X86/apx/sha1rnds4-intel.s
A llvm/test/MC/X86/apx/sha256msg1-att.s
A llvm/test/MC/X86/apx/sha256msg1-intel.s
A llvm/test/MC/X86/apx/sha256msg2-att.s
A llvm/test/MC/X86/apx/sha256msg2-intel.s
A llvm/test/MC/X86/apx/sha256rnds2-att.s
A llvm/test/MC/X86/apx/sha256rnds2-intel.s
M llvm/test/MC/X86/x86_64-asm-match.s
M llvm/test/TableGen/x86-fold-tables.inc
M llvm/utils/TableGen/X86FoldTablesEmitter.cpp
Log Message:
-----------
[X86][MC] Support Enc/Dec for EGPR for promoted SHA instruction (#75582)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted SHA instruction
in EVEX space.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
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