[all-commits] [llvm/llvm-project] 05abe8: [RISCV] Remove Zfbfmin dependency from Zvfbfmin. (...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 05abe8a7e8b466c656b8461e2c01338cf4eb82db
      https://github.com/llvm/llvm-project/commit/05abe8a7e8b466c656b8461e2c01338cf4eb82db
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-19 (Tue, 19 Dec 2023)

  Changed paths:
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s

  Log Message:
  -----------
  [RISCV] Remove Zfbfmin dependency from Zvfbfmin. (#75851)

Zvfbfmin does not have any scalar operands making this an unnecessary
dependency. The spec was just updated to remove this. See
https://github.com/riscv/riscv-bfloat16/commit/86d7a74f4b928e981f79f6d84a4592e6e9e4c0e9

This fixes a correctness issue where Xsfvfwmaccqqq was incorrectly
depending on Zfbfmin. The SiFive CPUs that support Xsfvfwmaccqqq do not
implement Zfbfmin, but do implement Zvfbfmin based on a previous
understanding that it only requires Zve32f. I've added tests for this
feature to raise the bar for adding dependencies to it in the future.