[all-commits] [llvm/llvm-project] 571d15: [RISCV][MISched] Set EnableIntervals to true for S...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 571d151deca57609fc08ee1721be51755a29870a
      https://github.com/llvm/llvm-project/commit/571d151deca57609fc08ee1721be51755a29870a
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-12-19 (Tue, 19 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    A llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir

  Log Message:
  -----------
  [RISCV][MISched] Set EnableIntervals to true for SiFive7 (#75681)

The SiFive7 scheduler model has been using AcquireAtCycles and
ReleaseAtCycles for some time. Without EnableIntervals, the scheduler
was not making decisions based on this information. This patch sets
EnableIntervals to true, and the test case demonstrates that the VADD
instructions can be issued one cycle earlier since the VCQ is not
reserved. This leads to better saturation of the SiFive7VA.