[all-commits] [llvm/llvm-project] 861600: [mlir][SparseTensor] Fix invalid IR in `ForallRewr...

[Matthias Springer via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 861600f1751b1a7e84cd99dd79361569542e9c1a
      https://github.com/llvm/llvm-project/commit/861600f1751b1a7e84cd99dd79361569542e9c1a
  Author: Matthias Springer <me at m-sp.org>
  Date:   2023-12-07 (Thu, 07 Dec 2023)

  Changed paths:
    M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp

  Log Message:
  -----------
  [mlir][SparseTensor] Fix invalid IR in `ForallRewriter` pattern (#74547)

The `ForallRewriter` pattern used to generate invalid IR:
```
mlir/test/Dialect/SparseTensor/GPU/gpu_combi.mlir:0:0: error: 'scf.for' op expects region #0 to have 0 or 1 blocks
mlir/test/Dialect/SparseTensor/GPU/gpu_combi.mlir:0:0: note: see current operation:
"scf.for"(%8, %2, %9) ({
^bb0(%arg5: index):
  // ...
  "scf.yield"() : () -> ()
^bb1(%10: index):  // no predecessors
  "scf.yield"() : () -> ()
}) : (index, index, index) -> ()
```

This commit fixes tests such as
`mlir/test/Dialect/SparseTensor/GPU/gpu_combi.mlir` when verifying the
IR after each pattern application (#74270).