[all-commits] [llvm/llvm-project] 1f283a: Reapply "RegisterCoalescer: Add implicit-def of su...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1f283a60a4bb896fa2d37ce00a3018924be82b9f
      https://github.com/llvm/llvm-project/commit/1f283a60a4bb896fa2d37ce00a3018924be82b9f
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-12-06 (Wed, 06 Dec 2023)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    A llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir
    A llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
    A llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir

  Log Message:
  -----------
  Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG"

This reverts commit 9e50c6e6b5741895f58f3e530004052844b6af9f. A few assertion and verifier
errors have been fixed in the coalescer and allocator, so hopefully this sticks this time.