[all-commits] [llvm/llvm-project] b0b69f: [mlir][ArmSME] More precisely model dataflow in Ar...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b0b69fd879a03f3d37b8cd78049d27939de23ce2
      https://github.com/llvm/llvm-project/commit/b0b69fd879a03f3d37b8cd78049d27939de23ce2
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2023-12-06 (Wed, 06 Dec 2023)

  Changed paths:
    M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
    M mlir/lib/Conversion/VectorToArmSME/VectorToArmSME.cpp
    M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
    M mlir/test/Dialect/ArmSME/arith-ops-to-sme.mlir
    M mlir/test/Dialect/ArmSME/vector-ops-to-sme.mlir

  Log Message:
  -----------
  [mlir][ArmSME] More precisely model dataflow in ArmSME to SCF lowerings (#73922)

Since #73253, loops over tiles in SSA form (i.e. loops that take
`iter_args` and yield a new tile) are supported, so this patch updates
ArmSME lowerings to this form. This is a NFC, as it still lowers to the
same intrinsics, but this makes IR less 'surprising' at a higher-level,
and may be recognised by more transforms.


Example:

IR before:
```mlir
scf.for %tile_slice_index = %c0 to %num_tile_slices step %c1 
{
   arm_sme.move_vector_to_tile_slice 
     %broadcast_to_1d, %tile, %tile_slice_index : 
     vector<[4]xi32> into vector<[4]x[4]xi32>
}
// ... later use %tile
```
IR now:
```mlir
%broadcast_to_tile = scf.for %tile_slice_index = %c0 to %num_tile_slices
    step %c1 iter_args(%iter_tile = %init_tile) -> (vector<[4]x[4]xi32>)
{
   %tile_update = arm_sme.move_vector_to_tile_slice
      %broadcast_to_1d, %iter_tile, %tile_slice_index :
      vector<[4]xi32> into vector<[4]x[4]xi32>
  scf.yield %tile_update : vector<[4]x[4]xi32>
}
// ... later use %broadcast_to_tile
```