[all-commits] [llvm/llvm-project] eecb99: [Tests] Add disjoint flag to some tests (NFC)

[Nikita Popov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: eecb99c5f66c8491766628a2925587e20f3b1dbd
      https://github.com/llvm/llvm-project/commit/eecb99c5f66c8491766628a2925587e20f3b1dbd
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2023-12-05 (Tue, 05 Dec 2023)

  Changed paths:
    M llvm/test/Analysis/CostModel/X86/interleaved-load-half.ll
    M llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
    M llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
    M llvm/test/Analysis/DependenceAnalysis/ExactRDIV.ll
    M llvm/test/Analysis/DependenceAnalysis/ExactSIV.ll
    M llvm/test/Analysis/DependenceAnalysis/GCD.ll
    M llvm/test/Analysis/LoopAccessAnalysis/stride-access-dependence.ll
    M llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll
    M llvm/test/Analysis/ScalarEvolution/nsw-offset.ll
    M llvm/test/Analysis/ScalarEvolution/sext-mul.ll
    M llvm/test/CodeGen/AArch64/aarch64-sched-store.ll
    M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smlad0.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smlad11.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smladx-1.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smlald0.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smlald2.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-1.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/smlaldx-2.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll
    M llvm/test/CodeGen/ARM/dsp-loop-indexing.ll
    M llvm/test/CodeGen/ARM/fpclamptosat.ll
    M llvm/test/CodeGen/ARM/loop-indexing.ll
    M llvm/test/CodeGen/ARM/shifter_operand.ll
    M llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
    M llvm/test/CodeGen/PowerPC/rematerializable-instruction-machine-licm.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/SystemZ/vec-load-element.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
    M llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
    M llvm/test/CodeGen/Thumb2/mve-tailpred-loopinvariant.ll
    M llvm/test/CodeGen/Thumb2/pacbti-m-vla.ll
    M llvm/test/CodeGen/WebAssembly/unrolled-mem-indices.ll
    M llvm/test/CodeGen/X86/2008-08-06-CmpStride.ll
    M llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
    M llvm/test/CodeGen/X86/avx512vnni-combine.ll
    M llvm/test/CodeGen/X86/avxvnni-combine.ll
    M llvm/test/CodeGen/X86/loop-strength-reduce4.ll
    M llvm/test/CodeGen/X86/lsr-addrecloops.ll
    M llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
    M llvm/test/CodeGen/X86/merge_store.ll
    M llvm/test/CodeGen/X86/optimize-max-0.ll
    M llvm/test/CodeGen/X86/unused_stackslots.ll
    M llvm/test/Transforms/IRCE/stride_more_than_1.ll
    M llvm/test/Transforms/IndVarSimplify/ashr-tripcount.ll
    M llvm/test/Transforms/IndVarSimplify/lcssa-preservation.ll
    M llvm/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
    M llvm/test/Transforms/IndVarSimplify/pr58702-invalidate-scev-when-replacing-congruent-phis.ll
    M llvm/test/Transforms/IndVarSimplify/pr64891.ll
    M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/complex-index.ll
    M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/extended-index.ll
    M llvm/test/Transforms/LoopIdiom/unroll-custom-dl.ll
    M llvm/test/Transforms/LoopIdiom/unroll.ll
    M llvm/test/Transforms/LoopInterchange/pr57148.ll
    M llvm/test/Transforms/LoopReroll/basic32iters.ll
    M llvm/test/Transforms/LoopReroll/indvar_with_ext.ll
    M llvm/test/Transforms/LoopReroll/reduction.ll
    M llvm/test/Transforms/LoopReroll/reroll_with_dbg.ll
    M llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll
    M llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll
    M llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll
    M llvm/test/Transforms/LoopStrengthReduce/X86/missing-phi-operand-update.ll
    M llvm/test/Transforms/LoopUnroll/X86/high-cost-expansion.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/strict-fadd.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
    M llvm/test/Transforms/LoopVectorize/X86/pr47437.ll
    M llvm/test/Transforms/LoopVectorize/X86/scatter_crash.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/pr39099.ll
    M llvm/test/Transforms/LoopVectorize/reduction-with-invariant-store.ll
    M llvm/test/Transforms/LoopVectorize/unroll_nonlatch.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
    M llvm/test/Transforms/SLPVectorizer/NVPTX/v2f16.ll
    M llvm/test/Transforms/SLPVectorizer/X86/compare-reduce.ll
    M llvm/test/Transforms/SLPVectorizer/X86/consecutive-access.ll
    M llvm/test/Transforms/SLPVectorizer/X86/hoist.ll
    M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
    M llvm/test/Transforms/SLPVectorizer/X86/in-tree-user.ll
    M llvm/test/Transforms/SLPVectorizer/X86/loopinvariant.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction.ll
    M llvm/test/Transforms/SLPVectorizer/X86/reduction2.ll
    M llvm/test/Transforms/SLPVectorizer/X86/remark_horcost.ll
    M llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
    M llvm/test/Transforms/SLPVectorizer/X86/scheduling.ll
    M llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll
    M llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll

  Log Message:
  -----------
  [Tests] Add disjoint flag to some tests (NFC)

These tests rely on SCEV looking recognizing an "or" with no common
bits as an "add". Add the disjoint flag to relevant or instructions
in preparation for switching SCEV to use the flag instead of the
ValueTracking query. The IR with disjoint flag matches what
InstCombine would produce.