[all-commits] [llvm/llvm-project] d9570b: [RISCV] Remove SiFive7PipeV and replace it with Si...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d9570babf1b253767a3a6c1450fa1b9e10b4e2f9
      https://github.com/llvm/llvm-project/commit/d9570babf1b253767a3a6c1450fa1b9e10b4e2f9
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-12-04 (Mon, 04 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s
    M llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
    M llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/disable-im.s
    M llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
    M llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s
    M llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s
    M llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s
    M llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s
    M llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s
    M llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s
    M llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s
    M llvm/test/tools/llvm-mca/RISCV/vle-vse.s
    M llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s
    M llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s

  Log Message:
  -----------
  [RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)

The Arithmetic, Load, and Store sequencers can accept instructions in
parallel. The PipeV blocked that from happening since it became busy if
any of the sequencers were busy. This change allows the sequencers to
accept instructions in parallel.

The VCQ accepts instructions from the the A Pipe and holds them until
the vector unit is ready to dequeue them. The unit dequeues up to one
instruction per cycle, in order, as soon as the sequencer for that type
of instruction is avaliable. This resource is meant to be used for 1
cycle by all vector instructions, to model that only one vector
instruction may be dequed at a time. The actual dequeueing into the
sequencer is modeled by the VA, VL, and VS sequencer resources below.
Each of them will only accept a single instruction at a time and remain
busy for the number of cycles associated with that instruction.