[all-commits] [llvm/llvm-project] cae650: [RISCV] Rework IDiv and FDiv pipes on SiFive7 (#73...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cae650ef3764288e1df47dcc48a5e180d1289ff4
      https://github.com/llvm/llvm-project/commit/cae650ef3764288e1df47dcc48a5e180d1289ff4
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-12-04 (Mon, 04 Dec 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s

  Log Message:
  -----------
  [RISCV] Rework IDiv and FDiv pipes on SiFive7 (#73970)

Set BufferSize=0 and remove Super pipes for these resources.