[all-commits] [llvm/llvm-project] 7ec4f6: [InstCombine] Infer disjoint flag on Or instructio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ec4f6094e54911794c142b5d88496a220d807d6
      https://github.com/llvm/llvm-project/commit/7ec4f6094e54911794c142b5d88496a220d807d6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-12-02 (Sat, 02 Dec 2023)

  Changed paths:
    M clang/test/Headers/__clang_hip_math.hip
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/2010-11-01-lshr-mask.ll
    M llvm/test/Transforms/InstCombine/add.ll
    M llvm/test/Transforms/InstCombine/and-or-not.ll
    M llvm/test/Transforms/InstCombine/and-or.ll
    M llvm/test/Transforms/InstCombine/and.ll
    M llvm/test/Transforms/InstCombine/apint-shift.ll
    M llvm/test/Transforms/InstCombine/binop-and-shifts.ll
    M llvm/test/Transforms/InstCombine/binop-of-displaced-shifts.ll
    M llvm/test/Transforms/InstCombine/bitcast-inselt-bitcast.ll
    M llvm/test/Transforms/InstCombine/bitreverse.ll
    M llvm/test/Transforms/InstCombine/bswap.ll
    M llvm/test/Transforms/InstCombine/cast-mul-select.ll
    M llvm/test/Transforms/InstCombine/cast.ll
    M llvm/test/Transforms/InstCombine/free-inversion.ll
    M llvm/test/Transforms/InstCombine/funnel.ll
    M llvm/test/Transforms/InstCombine/icmp-mul-and.ll
    M llvm/test/Transforms/InstCombine/icmp-of-xor-x.ll
    M llvm/test/Transforms/InstCombine/icmp.ll
    M llvm/test/Transforms/InstCombine/logical-select.ll
    M llvm/test/Transforms/InstCombine/masked-merge-or.ll
    M llvm/test/Transforms/InstCombine/masked-merge-xor.ll
    M llvm/test/Transforms/InstCombine/memcpy-from-global.ll
    M llvm/test/Transforms/InstCombine/mul-masked-bits.ll
    M llvm/test/Transforms/InstCombine/mul_full_32.ll
    M llvm/test/Transforms/InstCombine/mul_full_64.ll
    M llvm/test/Transforms/InstCombine/or-concat.ll
    M llvm/test/Transforms/InstCombine/or-shifted-masks.ll
    M llvm/test/Transforms/InstCombine/or.ll
    M llvm/test/Transforms/InstCombine/pr32686.ll
    M llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll
    M llvm/test/Transforms/InstCombine/select-icmp-and.ll
    M llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
    M llvm/test/Transforms/InstCombine/select.ll
    M llvm/test/Transforms/InstCombine/shift-shift.ll
    M llvm/test/Transforms/InstCombine/shift.ll
    M llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll
    M llvm/test/Transforms/InstCombine/sub-of-negatible.ll
    M llvm/test/Transforms/InstCombine/trunc-demand.ll
    M llvm/test/Transforms/InstCombine/trunc-inseltpoison.ll
    M llvm/test/Transforms/InstCombine/trunc.ll
    M llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-scalar.ll
    M llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-vector.ll
    M llvm/test/Transforms/InstCombine/xor.ll
    M llvm/test/Transforms/InstCombine/xor2.ll
    M llvm/test/Transforms/InstCombine/zext-or-icmp.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
    M llvm/test/Transforms/LoopVectorize/SystemZ/addressing.ll
    M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
    M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
    M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
    M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
    M llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll
    M llvm/test/Transforms/PhaseOrdering/X86/loadcombine.ll
    M llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
    M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll

  Log Message:
  -----------
  [InstCombine] Infer disjoint flag on Or instructions. (#72912)

The disjoint flag was recently added to IR in #72583

We already set it when we turn an add into an or. This patch sets it on Ors that weren't converted from an Add.