[all-commits] [llvm/llvm-project] b3e80d: [clang-format] Add space in Verilog tagged unions ...

[sstwcw via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b3e80d8ed251bfdad4a49fee19b8354eba407d1d
      https://github.com/llvm/llvm-project/commit/b3e80d8ed251bfdad4a49fee19b8354eba407d1d
  Author: sstwcw <su3e8a96kzlver at posteo.net>
  Date:   2023-12-02 (Sat, 02 Dec 2023)

  Changed paths:
    M clang/lib/Format/TokenAnnotator.cpp
    M clang/unittests/Format/FormatTestVerilog.cpp

  Log Message:
  -----------
  [clang-format] Add space in Verilog tagged unions (#71354)

In a tagged union expression, there should be a space between the field
name and the data. Previously, the tag could be recognized as part of a
dotted identifier or a struct literal, and the space would be omitted.