[all-commits] [llvm/llvm-project] d0a39e: [RISCV] default enable splitting regalloc between ...

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d0a39e617ba301a76d28e2d82e1f657999c9dcfb
      https://github.com/llvm/llvm-project/commit/d0a39e617ba301a76d28e2d82e1f657999c9dcfb
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2023-11-30 (Thu, 30 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

  Log Message:
  -----------
  [RISCV] default enable splitting regalloc between RVV and other (#72950)

This patch make riscv-split-regalloc as true by default. 

It will not affect the codegen result if it vector register allocation
doesn't exist. If there is the vector register allocation, it may affect
the non-rvv register LiveInterval's segment/weight. It will make the
allocation in a different order.