[all-commits] [llvm/llvm-project] 539e60: [X86] X86FixupVectorConstantsPass - consistently u...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 539e60c34a0a960f55eacf764f8c74d6c6c9d2b3
      https://github.com/llvm/llvm-project/commit/539e60c34a0a960f55eacf764f8c74d6c6c9d2b3
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-11-30 (Thu, 30 Nov 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-lzcnt-512.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll

  Log Message:
  -----------
  [X86] X86FixupVectorConstantsPass - consistently use non-DQI 128/256-bit subvector broadcasts

Without the predicate there's no benefit to using the DQI variants instead of the default AVX512F instructions


  Commit: 169db80e41936811c6744f2c513a1ed00d97f10e
      https://github.com/llvm/llvm-project/commit/169db80e41936811c6744f2c513a1ed00d97f10e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-11-30 (Thu, 30 Nov 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll
    M llvm/test/CodeGen/X86/2012-07-10-extload64.ll
    M llvm/test/CodeGen/X86/fold-load-vec.ll
    M llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
    M llvm/test/CodeGen/X86/half.ll
    M llvm/test/CodeGen/X86/nontemporal-3.ll
    M llvm/test/CodeGen/X86/pr13577.ll
    M llvm/test/CodeGen/X86/pr41619.ll
    M llvm/test/CodeGen/X86/vec_zero_cse.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

  Log Message:
  -----------
  [X86] Canonicalize fp zero vectors from bitcasted integer zero vectors

Generic code is supposed to handle this but can be blocked by hasOneUse checks.

Noticed while investigating #26392


Compare: https://github.com/llvm/llvm-project/compare/899fd0cd6604...169db80e4193