[all-commits] [llvm/llvm-project] 4d8012: [AArch64] Teach areMemAccessesTriviallyDisjoint ab...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4d8012259846274c6122b3befdff32d4c3010f7c
      https://github.com/llvm/llvm-project/commit/4d8012259846274c6122b3befdff32d4c3010f7c
  Author: David Green <david.green at arm.com>
  Date:   2023-11-30 (Thu, 30 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/lib/Target/AArch64/AArch64InstrInfo.h
    M llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp
    M llvm/test/CodeGen/AArch64/alloca-load-store-scalable-array.ll
    M llvm/test/CodeGen/AArch64/sve-aliasing.ll
    A llvm/test/CodeGen/AArch64/sve-aliasing.mir
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll

  Log Message:
  -----------
  [AArch64] Teach areMemAccessesTriviallyDisjoint about scalable widths. (#73655)

The base change here is to change getMemOperandWithOffsetWidth to return
a TypeSize Width, which in turn allows areMemAccessesTriviallyDisjoint
to reason about trivially disjoint widths.