[all-commits] [llvm/llvm-project] 6976da: [RISCV][GISEL] regbankselect and instruction-selec...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6976dac09db6dab3ef9eb68f1d19b70aa2847773
      https://github.com/llvm/llvm-project/commit/6976dac09db6dab3ef9eb68f1d19b70aa2847773
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-11-30 (Thu, 30 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/implicit-def-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/implicit-def-rv64.mir

  Log Message:
  -----------
  [RISCV][GISEL] regbankselect and instruction-select for G_IMPLICIT_DEF (#73060)

This is similar to the selection of G_IMPLICIT_DEF in AArch64.
Regbankselect may need to be improved in a future patch.